1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos SoC has many buses for data transfer between DRAM and
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
17 which are able to change the clock frequency of the bus in runtime. To
18 monitor the usage of each bus in runtime, the driver uses the PPMU (Platform
19 Performance Monitoring Unit), which is able to measure the current load of
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
23 The each AXI bus has the owned source clock but, has not the only owned power
24 line. The power line might be shared among one more sub-blocks. So, we can
25 divide into two type of device as the role of each sub-block. There are two
26 type of bus devices as following::
30 Basically, parent and passive bus device share the same power line. The
31 parent bus device can only change the voltage of shared power line and the
32 rest bus devices (passive bus device) depend on the decision of the parent
33 bus device. If there are three blocks which share the VDD_xxx power line,
34 Only one block should be parent device and then the rest blocks should depend
35 on the parent device as passive device.
37 VDD_xxx |--- A block (parent)
38 |--- B block (passive)
39 |--- C block (passive)
41 There are a little different composition among Exynos SoC because each Exynos
42 SoC has different sub-blocks. Therefore, such difference should be specified
43 in devicetree file instead of each device driver. In result, this driver is
44 able to support the bus frequency for all Exynos SoCs.
46 Detailed correlation between sub-blocks and power line according
48 - In case of Exynos3250, there are two power line as following::
49 VDD_MIF |--- DMC (Dynamic Memory Controller)
51 VDD_INT |--- LEFTBUS (parent device)
63 - MIF bus's frequency/voltage table
64 -----------------------
66 -----------------------
72 -----------------------
74 - INT bus's frequency/voltage table
75 ----------------------------------------------------------
76 |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP |PERIL ||VDD_INT |
77 | name| |LCD0 | | | || |
80 ----------------------------------------------------------
81 |Mode |*parent|passive |passive|passive|passive|| |
82 ----------------------------------------------------------
83 |Lv |Frequency ||Voltage |
84 ----------------------------------------------------------
85 |L1 |50000 |50000 |50000 |50000 |50000 ||900000 |
86 |L2 |80000 |80000 |80000 |80000 |80000 ||900000 |
87 |L3 |100000 |100000 |100000 |100000 |100000 ||1000000 |
88 |L4 |134000 |134000 |200000 |200000 | ||1000000 |
89 |L5 |200000 |200000 |400000 |300000 | ||1000000 |
90 ----------------------------------------------------------
92 - In case of Exynos4210, there is one power line as following::
93 VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
109 - In case of Exynos4x12, there are two power line as following::
110 VDD_MIF |--- DMC (Dynamic Memory Controller)
112 VDD_INT |--- LEFTBUS (parent device)
127 - In case of Exynos5422, there are two power line as following::
128 VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
131 VDD_INT |--- NoC_Core (parent device)
146 - In case of Exynos5433, there is VDD_INT power line as following::
147 VDD_INT |--- G2D (parent device)
156 |--- PERIS (Fixed clock rate)
157 |--- PERIC (Fixed clock rate)
158 |--- FSYS (Fixed clock rate)
173 $ref: /schemas/types.yaml#/definitions/phandle
175 Parent bus device. Valid and required only for the passive bus devices.
178 $ref: /schemas/types.yaml#/definitions/phandle-array
182 Devfreq-event device to monitor the current utilization of buses. Valid
183 and required only for the parent bus devices.
185 exynos,saturation-ratio:
186 $ref: /schemas/types.yaml#/definitions/uint32
188 Percentage value which is used to calibrate the performance count against
189 total cycle count. Valid only for the parent bus devices.
191 '#interconnect-cells':
198 operating-points-v2: true
200 samsung,data-clock-ratio:
201 $ref: /schemas/types.yaml#/definitions/uint32
204 Ratio of the data throughput in B/s to minimum data clock frequency in
209 Main bus power rail. Valid and required only for the parent bus devices.
215 - operating-points-v2
217 additionalProperties: false
221 #include <dt-bindings/clock/exynos3250.h>
224 compatible = "samsung,exynos-bus";
225 clocks = <&cmu_dmc CLK_DIV_DMC>;
227 operating-points-v2 = <&bus_dmc_opp_table>;
228 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
229 vdd-supply = <&buck1_reg>;
232 ppmu_dmc0: ppmu@106a0000 {
233 compatible = "samsung,exynos-ppmu";
234 reg = <0x106a0000 0x2000>;
236 ppmu_dmc0_3: ppmu-event3-dmc0 {
237 event-name = "ppmu-event3-dmc0";
242 bus_leftbus: bus-leftbus {
243 compatible = "samsung,exynos-bus";
244 clocks = <&cmu CLK_DIV_GDL>;
246 operating-points-v2 = <&bus_leftbus_opp_table>;
247 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
248 vdd-supply = <&buck3_reg>;
252 compatible = "samsung,exynos-bus";
253 clocks = <&cmu CLK_DIV_GDR>;
255 operating-points-v2 = <&bus_leftbus_opp_table>;
256 devfreq = <&bus_leftbus>;
261 compatible = "samsung,exynos-bus";
262 clocks = <&clock CLK_DIV_DMC>;
264 operating-points-v2 = <&bus_dmc_opp_table>;
265 samsung,data-clock-ratio = <4>;
266 #interconnect-cells = <0>;
267 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
268 vdd-supply = <&buck1_reg>;
271 leftbus: bus-leftbus {
272 compatible = "samsung,exynos-bus";
273 clocks = <&clock CLK_DIV_GDL>;
275 operating-points-v2 = <&bus_leftbus_opp_table>;
276 interconnects = <&dmc>;
277 #interconnect-cells = <0>;
278 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
279 vdd-supply = <&buck3_reg>;
282 display: bus-display {
283 compatible = "samsung,exynos-bus";
284 clocks = <&clock CLK_DIV_ACLK_266>;
286 operating-points-v2 = <&bus_display_opp_table>;
287 interconnects = <&leftbus &dmc>;
288 #interconnect-cells = <0>;
289 devfreq = <&leftbus>;