1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: STMicroelectronics STM32 ADC bindings
10 STM32 ADC is a successive approximation analog-to-digital converter.
11 It has several multiplexed input channels. Conversions can be performed
12 in single, continuous, scan or discontinuous mode. Result of the ADC is
13 stored in a left-aligned or right-aligned 32-bit data register.
14 Conversions can be launched in software or using hardware triggers.
16 The analog watchdog feature allows the application to detect if the input
17 voltage goes beyond the user-defined, higher or lower thresholds.
19 Each STM32 ADC block can have up to 3 ADC instances.
22 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
29 - st,stm32mp1-adc-core
36 One or more interrupts for ADC block, depending on part used:
37 - stm32f4 and stm32h7 share a common ADC interrupt line.
38 - stm32mp1 has two separate interrupt lines, one for each ADC within
47 Core can use up to two clocks, depending on part used:
48 - "adc" clock: for the analog circuitry, common to all ADCs.
49 It's required on stm32f4.
50 It's optional on stm32h7 and stm32mp1.
51 - "bus" clock: for registers access, common to all ADCs.
52 It's not present on stm32f4.
53 It's required on stm32h7 and stm32mp1.
59 Allow to specify desired max clock rate used by analog circuitry.
62 description: Phandle to the vdda input analog voltage.
65 description: Phandle to the vref input analog reference voltage.
69 Phandle to the embedded booster regulator that can be used to supply ADC
70 analog input switches on stm32h7 and stm32mp1.
74 Phandle to the vdd input voltage. It can be used to supply ADC analog
75 input switches on stm32mp1.
79 Phandle to system configuration controller. It can be used to control the
80 analog circuitry on stm32mp1.
81 $ref: "/schemas/types.yaml#/definitions/phandle-array"
83 interrupt-controller: true
99 const: st,stm32f4-adc-core
111 - description: interrupt line common for all ADCs
118 booster-supply: false
128 const: st,stm32h7-adc-core
144 - description: interrupt line common for all ADCs
159 const: st,stm32mp1-adc-core
175 - description: interrupt line for ADC1
176 - description: interrupt line for ADC2
183 additionalProperties: false
193 - interrupt-controller
202 An ADC block node should contain at least one subnode, representing an
203 ADC instance available on the machine.
214 Offset of ADC instance in ADC block. Valid values are:
217 - 0x200: ADC3 (stm32f4 only)
231 IRQ Line for the ADC instance. Valid values are:
234 - 2 for adc@200 (stm32f4 only)
239 Input clock private to this ADC instance. It's required only on
240 stm32f4, that has per instance clock input for registers access.
244 description: RX DMA Channel
250 assigned-resolution-bits:
252 Resolution (bits) to use for conversions:
253 - can be 6, 8, 10 or 12 on stm32f4
254 - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
258 List of single-ended channels muxed for this ADC. It can have up to:
259 - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
260 - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
262 $ref: /schemas/types.yaml#/definitions/uint32-array
265 st,adc-diff-channels:
267 List of differential channels muxed for this ADC. Some channels can
268 be configured as differential instead of single-ended on stm32h7 and
269 on stm32mp1. Positive and negative inputs pairs are listed:
270 <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
272 Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
273 required if no adc generic channel is defined. These legacy channel
274 properties are exclusive with adc generic channel bindings.
275 Both properties can be used together. Some channels can be
276 used as single-ended and some other ones as differential (mixed). But
277 channels can't be configured both as single-ended and differential.
278 $ref: /schemas/types.yaml#/definitions/uint32-matrix
282 "vinp" indicates positive input number
286 "vinn" indicates negative input number
291 st,min-sample-time-nsecs:
293 Minimum sampling time in nanoseconds. Depending on hardware (board)
294 e.g. high/low analog input source impedance, fine tune of ADC
295 sampling time may be recommended. This can be either one value or an
296 array that matches "st,adc-channels" and/or "st,adc-diff-channels"
297 list, to set sample time resp. for all channels, or independently for
299 $ref: /schemas/types.yaml#/definitions/uint32-array
304 - description: Phandle to the calibration vrefint data provided by otp
311 "^channel@([0-9]|1[0-9])$":
314 description: Represents the external channels which are connected to the ADC.
324 Unique name to identify which channel this is.
325 Reserved label names "vddcore", "vrefint" and "vbat"
326 are used to identify internal channels with matching names.
329 $ref: /schemas/types.yaml#/definitions/uint32-array
334 st,min-sample-time-ns:
336 Minimum sampling time in nanoseconds. Depending on hardware (board)
337 e.g. high/low analog input source impedance, fine tune of ADC
338 sampling time may be recommended.
343 additionalProperties: false
350 const: st,stm32f4-adc
364 assigned-resolution-bits:
375 st,adc-diff-channels: false
377 st,min-sample-time-nsecs:
405 assigned-resolution-bits:
406 enum: [8, 10, 12, 14, 16]
416 st,min-sample-time-nsecs:
422 additionalProperties: false
428 - '#io-channel-cells'
432 // Example 1: with stm32f429, ADC1, single-ended channel 8
433 adc123: adc@40012000 {
434 compatible = "st,stm32f4-adc-core";
435 reg = <0x40012000 0x400>;
437 clocks = <&rcc 0 168>;
439 st,max-clk-rate-hz = <36000000>;
440 vdda-supply = <&vdda>;
441 vref-supply = <&vref>;
442 interrupt-controller;
443 #interrupt-cells = <1>;
444 #address-cells = <1>;
447 compatible = "st,stm32f4-adc";
448 #io-channel-cells = <1>;
450 clocks = <&rcc 0 168>;
451 interrupt-parent = <&adc123>;
453 st,adc-channels = <8>;
454 dmas = <&dma2 0 0 0x400 0x0>;
456 assigned-resolution-bits = <8>;
459 // other adc child nodes follow...
463 // Example 2: with stm32mp157c to setup ADC1 with:
464 // - channels 0 & 1 as single-ended
465 // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
466 #include <dt-bindings/interrupt-controller/arm-gic.h>
467 #include <dt-bindings/clock/stm32mp1-clks.h>
468 adc12: adc@48003000 {
469 compatible = "st,stm32mp1-adc-core";
470 reg = <0x48003000 0x400>;
471 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
474 clock-names = "bus", "adc";
475 booster-supply = <&booster>;
477 vdda-supply = <&vdda>;
478 vref-supply = <&vref>;
479 st,syscfg = <&syscfg>;
480 interrupt-controller;
481 #interrupt-cells = <1>;
482 #address-cells = <1>;
485 compatible = "st,stm32mp1-adc";
486 #io-channel-cells = <1>;
488 interrupt-parent = <&adc12>;
490 st,adc-channels = <0 1>;
491 st,adc-diff-channels = <2 6>, <3 7>;
492 st,min-sample-time-nsecs = <5000>;
493 dmas = <&dmamux1 9 0x400 0x05>;
497 // other adc child node follow...
501 // Example 3: with stm32mp157c to setup ADC2 with:
502 // - internal channels 13, 14, 15.
503 #include <dt-bindings/interrupt-controller/arm-gic.h>
504 #include <dt-bindings/clock/stm32mp1-clks.h>
505 adc122: adc@48003000 {
506 compatible = "st,stm32mp1-adc-core";
507 reg = <0x48003000 0x400>;
508 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
511 clock-names = "bus", "adc";
512 booster-supply = <&booster>;
514 vdda-supply = <&vdda>;
515 vref-supply = <&vref>;
516 st,syscfg = <&syscfg>;
517 interrupt-controller;
518 #interrupt-cells = <1>;
519 #address-cells = <1>;
522 compatible = "st,stm32mp1-adc";
523 #io-channel-cells = <1>;
526 #address-cells = <1>;
531 st,min-sample-time-ns = <9000>;
536 st,min-sample-time-ns = <9000>;
541 st,min-sample-time-ns = <9000>;