1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L ADC
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 A/D Converter block is a successive approximation analog-to-digital converter
14 with a 12-bit accuracy. Up to eight analog input channels can be selected.
15 Conversions can be performed in single or repeat mode. Result of the ADC is
16 stored in a 32-bit data register corresponding to each channel.
22 - renesas,r9a07g043-adc # RZ/G2UL and RZ/Five
23 - renesas,r9a07g044-adc # RZ/G2L
24 - renesas,r9a07g054-adc # RZ/V2L
25 - const: renesas,rzg2l-adc
35 - description: converter clock
36 - description: peripheral clock
75 Represents the external channels which are connected to the ADC.
85 additionalProperties: false
92 const: renesas,r9a07g043-adc
95 "^channel@[2-7]$": false
109 additionalProperties: false
113 #include <dt-bindings/clock/r9a07g044-cpg.h>
114 #include <dt-bindings/interrupt-controller/arm-gic.h>
117 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
118 reg = <0x10059000 0x400>;
119 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
120 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
121 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
122 clock-names = "adclk", "pclk";
123 power-domains = <&cpg>;
124 resets = <&cpg R9A07G044_ADC_PRESETN>,
125 <&cpg R9A07G044_ADC_ADRST_N>;
126 reset-names = "presetn", "adrst-n";
128 #address-cells = <1>;