1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/iio/adc/fsl,vf610-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADC found on Freescale vf610 and similar SoCs
10 - Haibo Chen <haibo.chen@nxp.com>
13 ADCs found on vf610/i.MX6slx and upward SoCs from Freescale.
22 - const: fsl,vf610-adc
24 - const: fsl,vf610-adc
33 description: ADC source clock (ipg clock)
40 description: ADC reference voltage supply.
42 fsl,adck-max-frequency:
43 $ref: /schemas/types.yaml#/definitions/uint32-array
47 Maximum frequencies from datasheet operating requirements.
48 Three values necessary to cover the 3 conversion modes.
49 * Frequency in normal mode (ADLPC=0, ADHSC=0)
50 * Frequency in high-speed mode (ADLPC=0, ADHSC=1)
51 * Frequency in low-power mode (ADLPC=1, ADHSC=0)
54 $ref: /schemas/types.yaml#/definitions/uint32
56 Minimum sampling time in nanoseconds. This value has
57 to be chosen according to the conversion mode and the connected analog
58 source resistance (R_as) and capacitance (C_as). Refer the datasheet's
59 operating requirements. A safe default across a wide range of R_as and
60 C_as as well as conversion modes is 1000ns.
73 additionalProperties: false
77 #include <dt-bindings/clock/vf610-clock.h>
79 compatible = "fsl,vf610-adc";
80 reg = <0x4003b000 0x1000>;
81 interrupts = <0 53 0x04>;
82 clocks = <&clks VF610_CLK_ADC0>;
84 fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>;
85 vref-supply = <®_vcc_3v3_mcu>;
86 min-sample-time = <10000>;