GNU Linux-libre 4.19.295-gnu1
[releases.git] / Documentation / devicetree / bindings / iio / adc / amlogic,meson-saradc.txt
1 * Amlogic Meson SAR (Successive Approximation Register) A/D converter
2
3 Required properties:
4 - compatible:   depending on the SoC this should be one of:
5                         - "amlogic,meson8-saradc" for Meson8
6                         - "amlogic,meson8b-saradc" for Meson8b
7                         - "amlogic,meson8m2-saradc" for Meson8m2
8                         - "amlogic,meson-gxbb-saradc" for GXBB
9                         - "amlogic,meson-gxl-saradc" for GXL
10                         - "amlogic,meson-gxm-saradc" for GXM
11                         - "amlogic,meson-axg-saradc" for AXG
12                 along with the generic "amlogic,meson-saradc"
13 - reg:          the physical base address and length of the registers
14 - interrupts:   the interrupt indicating end of sampling
15 - clocks:       phandle and clock identifier (see clock-names)
16 - clock-names:  mandatory clocks:
17                         - "clkin" for the reference clock (typically XTAL)
18                         - "core" for the SAR ADC core clock
19                 optional clocks:
20                         - "adc_clk" for the ADC (sampling) clock
21                         - "adc_sel" for the ADC (sampling) clock mux
22 - vref-supply:  the regulator supply for the ADC reference voltage
23 - #io-channel-cells: must be 1, see ../iio-bindings.txt
24
25 Example:
26         saradc: adc@8680 {
27                 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
28                 #io-channel-cells = <1>;
29                 reg = <0x0 0x8680 0x0 0x34>;
30                 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
31                 clocks = <&xtal>,
32                          <&clkc CLKID_SAR_ADC>,
33                          <&clkc CLKID_SANA>,
34                          <&clkc CLKID_SAR_ADC_CLK>,
35                          <&clkc CLKID_SAR_ADC_SEL>;
36                 clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
37         };