1 I2C for Atmel platforms
4 - compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
5 "atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
6 "atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c"
7 - reg: physical base address of the controller and length of memory mapped
9 - interrupts: interrupt number to the cpu.
10 - #address-cells = <1>;
12 - clocks: phandles to input clocks.
15 - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
16 - dmas: A list of two dma specifiers, one for each entry in dma-names.
17 - dma-names: should contain "tx" and "rx".
18 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
19 capable I2C controllers.
20 - i2c-sda-hold-time-ns: TWD hold time, only available for "atmel,sama5d4-i2c"
21 and "atmel,sama5d2-i2c".
22 - Child nodes conforming to i2c bus binding
27 compatible = "atmel,at91sam9g20-i2c";
28 reg = <0xfff84000 0x100>;
29 interrupts = <12 4 6>;
33 clock-frequency = <400000>;
36 compatible = "24c512";
43 compatible = "atmel,sama5d2-i2c";
44 reg = <0xf8034600 0x100>;
45 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
47 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
48 AT91_XDMAC_DT_PERID(11)>,
50 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
51 AT91_XDMAC_DT_PERID(12)>;
52 dma-names = "tx", "rx";
56 atmel,fifo-size = <16>;
57 i2c-sda-hold-time-ns = <336>;
60 compatible = "wm8731";