1 Device tree configuration for the I2C busses on the AST24XX and AST25XX SoCs.
4 - #address-cells : should be 1
5 - #size-cells : should be 0
6 - reg : address offset and range of bus
7 - compatible : should be "aspeed,ast2400-i2c-bus"
8 or "aspeed,ast2500-i2c-bus"
9 - clocks : root clock of bus, should reference the APB
10 clock in the second cell
11 - resets : phandle to reset controller with the reset number in
13 - interrupts : interrupt number
16 - bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not
18 - multi-master : states that there is another master active on this bus.
23 compatible = "simple-bus";
26 ranges = <0 0x1e78a000 0x1000>;
28 i2c_ic: interrupt-controller@0 {
29 #interrupt-cells = <1>;
30 compatible = "aspeed,ast2400-i2c-ic";
39 #interrupt-cells = <1>;
41 compatible = "aspeed,ast2400-i2c-bus";
42 clocks = <&syscon ASPEED_CLK_APB>;
43 resets = <&syscon ASPEED_RESET_I2C>;
44 bus-frequency = <100000>;
46 interrupt-parent = <&i2c_ic>;