1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
5 $id: http://devicetree.org/schemas/i2c/atmel,at91sam-i2c.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: I2C for Atmel/Microchip platforms
11 - Alexandre Belloni <alexandre.belloni@bootlin.com>
18 - atmel,at91rm9200-i2c
19 - atmel,at91sam9261-i2c
20 - atmel,at91sam9260-i2c
21 - atmel,at91sam9g20-i2c
22 - atmel,at91sam9g10-i2c
23 - atmel,at91sam9x5-i2c
26 - microchip,sam9x60-i2c
28 - const: microchip,sama7g5-i2c
29 - const: microchip,sam9x60-i2c
51 - description: TX DMA Channel Specifier
52 - description: RX DMA Channel Specifier
60 $ref: /schemas/types.yaml#/definitions/uint32
62 Maximum number of data the RX and TX FIFOs can store for
63 FIFO capable I2C controllers.
78 - $ref: "i2c-controller.yaml"
86 - microchip,sam9x60-i2c
87 - microchip,sama7g5-i2c
95 unevaluatedProperties: false
99 #include <dt-bindings/interrupt-controller/irq.h>
100 #include <dt-bindings/dma/at91.h>
101 #include <dt-bindings/gpio/gpio.h>
104 compatible = "atmel,at91sam9g20-i2c";
105 reg = <0xfff84000 0x100>;
106 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
107 #address-cells = <1>;
109 clocks = <&twi0_clk>;
110 clock-frequency = <400000>;
113 compatible = "atmel,24c512";
120 compatible = "atmel,sama5d2-i2c";
121 reg = <0xf8034600 0x100>;
122 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
124 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
125 AT91_XDMAC_DT_PERID(11)>,
127 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
128 AT91_XDMAC_DT_PERID(12)>;
129 dma-names = "tx", "rx";
130 #address-cells = <1>;
133 atmel,fifo-size = <16>;
134 i2c-sda-hold-time-ns = <336>;
135 pinctrl-names = "default", "gpio";
136 pinctrl-0 = <&pinctrl_i2c0>;
137 pinctrl-1 = <&pinctrl_i2c0_gpio>;
138 sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
139 scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
142 compatible = "atmel,24c02";