1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra20-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra20 - Tegra210)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
22 - nvidia,tegra114-gpio
23 - nvidia,tegra124-gpio
24 - nvidia,tegra210-gpio
25 - const: nvidia,tegra30-gpio
31 description: The interrupt outputs from the controller. For Tegra20,
32 there should be 7 interrupts specified, and for Tegra30, there should
33 be 8 interrupts specified.
36 description: The first cell is the pin number and the second cell is used
37 to specify the GPIO polarity (0 = active high, 1 = active low).
47 Should be 2. The first cell is the GPIO number. The second cell is
48 used to specify flags:
50 bits[3:0] trigger type and level flags:
51 1 = low-to-high edge triggered.
52 2 = high-to-low edge triggered.
53 4 = active high level-sensitive.
54 8 = active low level-sensitive.
56 Valid combinations are 1, 2, 3, 4, 8.
59 interrupt-controller: true
66 const: nvidia,tegra30-gpio
85 - interrupt-controller
94 #include <dt-bindings/interrupt-controller/arm-gic.h>
97 compatible = "nvidia,tegra20-gpio";
98 reg = <0x6000d000 0x1000>;
99 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
108 #interrupt-cells = <2>;
109 interrupt-controller;