1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controller for Davinci and keystone devices
10 - Keerthy <j-keerthy@ti.com>
21 - const: ti,keystone-gpio
36 description: strings describing the names of each gpio line.
43 first cell is the pin number and second cell is used to specify optional parameters (unused).
47 The interrupts are specified as per the interrupt parent. Only banked
48 or unbanked IRQs are supported at a time. If the interrupts are
49 banked then provide list of interrupts corresponding to each bank, else
50 provide the list of interrupts for each gpio.
55 $ref: /schemas/types.yaml#/definitions/uint32
56 description: The number of GPIO pins supported consecutively.
59 ti,davinci-gpio-unbanked:
60 $ref: /schemas/types.yaml#/definitions/uint32
61 description: The number of GPIOs that have an individual interrupt line to processor.
70 interrupt-controller: true
79 "^(.+-hog(-[0-9]+)?)$":
92 - ti,davinci-gpio-unbanked
96 additionalProperties: false
100 #include<dt-bindings/interrupt-controller/arm-gic.h>
102 gpio0: gpio@2603000 {
103 compatible = "ti,k2g-gpio", "ti,keystone-gpio";
104 reg = <0x02603000 0x100>;
107 interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
108 <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
109 <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
110 <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
111 <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
112 <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
113 <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
114 <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
115 <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
116 interrupt-controller;
117 #interrupt-cells = <2>;
119 ti,davinci-gpio-unbanked = <0>;
120 clocks = <&k2g_clks 0x001b 0x0>;
121 clock-names = "gpio";
125 #include<dt-bindings/interrupt-controller/arm-gic.h>
127 gpio1: gpio@260bf00 {
128 compatible = "ti,keystone-gpio";
129 reg = <0x0260bf00 0x100>;
132 /* HW Interrupts mapped to GPIO pins */
133 interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
134 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
135 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
136 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
137 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
138 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
139 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
140 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
141 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
142 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
143 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
144 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
145 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
146 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
147 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
148 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
149 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
150 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
151 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
152 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
153 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
154 <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
155 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
156 <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
157 <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
158 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
159 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
160 <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
161 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
162 <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
163 <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
164 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
166 clock-names = "gpio";
168 ti,davinci-gpio-unbanked = <32>;
172 wkup_gpio0: gpio0@42110000 {
173 compatible = "ti,am654-gpio", "ti,keystone-gpio";
174 reg = <0x42110000 0x100>;
177 interrupt-parent = <&intr_wkup_gpio>;
178 interrupts = <60>, <61>, <62>, <63>;
179 interrupt-controller;
180 #interrupt-cells = <2>;
182 ti,davinci-gpio-unbanked = <0>;
183 clocks = <&k3_clks 59 0>;
184 clock-names = "gpio";