1 Xilinx Slave Serial SPI FPGA Manager
3 Xilinx Spartan-6 FPGAs support a method of loading the bitstream over
4 what is referred to as "slave serial" interface.
5 The slave serial link is not technically SPI, and might require extra
6 circuits in order to play nicely with other SPI slaves on the same bus.
8 See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
11 - compatible: should contain "xlnx,fpga-slave-serial"
12 - reg: spi chip select of the FPGA
13 - prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
14 - done-gpios: config status pin (referred to as DONE in the manual)
16 Example for full FPGA configuration:
19 compatible = "fpga-region";
20 fpga-mgr = <&fpga_mgr_spi>;
21 #address-cells = <0x1>;
26 compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
27 pinctrl-0 = <&spi0_pins>;
28 pinctrl-names = "default";
33 clocks = <&coreclk 0>;
35 fpga_mgr_spi: fpga-mgr@0 {
36 compatible = "xlnx,fpga-slave-serial";
37 spi-max-frequency = <60000000>;
40 done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
41 prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;