1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8 DSP core
10 - Daniel Baluta <daniel.baluta@nxp.com>
11 - Shengjiu Wang <shengjiu.wang@nxp.com>
14 Some boards from i.MX8 family contain a DSP core used for
15 advanced pre- and post- audio processing.
34 - description: ipg clock
35 - description: ocram clock
36 - description: core clock
37 - description: debug interface clock
38 - description: message unit clock
52 List of phandle and PM domain specifier as documented in
53 Documentation/devicetree/bindings/power/power_domain.txt
59 List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
60 or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB
61 (see mailbox/fsl,mu.txt)
71 phandle to a node describing reserved memory (System RAM memory)
72 used by DSP (see bindings/reserved-memory/reserved-memory.txt)
78 Default name of the firmware to load to the remote processor.
81 $ref: /schemas/types.yaml#/definitions/phandle
83 Phandle to syscon block which provide access for processor enablement
147 additionalProperties: false
151 #include <dt-bindings/firmware/imx/rsrc.h>
152 #include <dt-bindings/clock/imx8-clock.h>
154 compatible = "fsl,imx8qxp-dsp";
155 reg = <0x596e8000 0x88000>;
156 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
157 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
158 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
159 clock-names = "ipg", "ocram", "core";
160 power-domains = <&pd IMX_SC_R_MU_13A>,
161 <&pd IMX_SC_R_MU_13B>,
163 <&pd IMX_SC_R_DSP_RAM>;
164 mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
165 mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
166 memory-region = <&dsp_reserved>;
169 #include <dt-bindings/clock/imx8mp-clock.h>
170 dsp_reserved: dsp@92400000 {
171 reg = <0x92400000 0x1000000>;
174 dsp_vdev0vring0: vdev0vring0@942f0000 {
175 reg = <0x942f0000 0x8000>;
178 dsp_vdev0vring1: vdev0vring1@942f8000 {
179 reg = <0x942f8000 0x8000>;
182 dsp_vdev0buffer: vdev0buffer@94300000 {
183 compatible = "shared-dma-pool";
184 reg = <0x94300000 0x100000>;
189 compatible = "fsl,imx8mp-hifi4";
190 reg = <0x3b6e8000 0x88000>;
191 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
192 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,
193 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
194 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>;
195 clock-names = "ipg", "ocram", "core", "debug";
196 firmware-name = "/*(DEBLOBBED)*/";
197 power-domains = <&audiomix_pd>;
198 mbox-names = "tx", "rx", "rxdb";
202 memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
203 <&dsp_vdev0vring1>, <&dsp_reserved>;
204 fsl,dsp-ctrl = <&audio_blk_ctrl>;