1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
11 DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
12 channels for a video stream, 1 channel for a graphics stream, and 2 channels
16 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 - $ref: "../dma-controller.yaml#"
25 The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
26 for a list of channel IDs).
29 const: xlnx,zynqmp-dpdma
38 description: The AXI clock
52 additionalProperties: false
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
58 dma: dma-controller@fd4c0000 {
59 compatible = "xlnx,zynqmp-dpdma";
60 reg = <0xfd4c0000 0x1000>;
61 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
62 interrupt-parent = <&gic>;
63 clocks = <&dpdma_clk>;
64 clock-names = "axi_clk";