1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: "dma-controller.yaml#"
19 - const: snps,dma-spear1340
22 - renesas,r9a06g032-dma
23 - const: renesas,rzn1-dma
30 First cell is a phandle pointing to the DMA controller. Second one is
31 the DMA request line number. Third cell is the memory master identifier
32 for transfers on dynamically allocated channel. Fourth cell is the
33 peripheral master identifier for transfers on an allocated channel. Fifth
34 cell is an optional mask of the DMA channels permitted to be allocated
35 for the corresponding client device.
47 description: AHB interface reference clock.
52 Number of DMA channels supported by the controller. In case if
53 not specified the driver will try to auto-detect this and
54 the rest of the optional parameters.
63 $ref: /schemas/types.yaml#/definitions/uint32
65 Number of DMA masters supported by the controller. In case if
66 not specified the driver will try to auto-detect this and
67 the rest of the optional parameters.
71 chan_allocation_order:
72 $ref: /schemas/types.yaml#/definitions/uint32
74 DMA channels allocation order specifier. Zero means ascending order
75 (first free allocated), while one - descending (last free allocated).
80 $ref: /schemas/types.yaml#/definitions/uint32
82 DMA channels priority order. Zero means ascending channels priority
83 so the very first channel has the highest priority. While 1 means
84 descending priority (the last channel has the highest priority).
89 $ref: /schemas/types.yaml#/definitions/uint32
90 description: Maximum block size supported by the DMA controller.
91 enum: [3, 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095]
94 $ref: /schemas/types.yaml#/definitions/uint32-array
95 description: Data bus width per each DMA master in bytes.
102 $ref: /schemas/types.yaml#/definitions/uint32-array
105 Data bus width per each DMA master in (2^n * 8) bits. This property is
106 deprecated. It' usage is discouraged in favor of data-width one. Moreover
107 the property incorrectly permits to define data-bus width of 8 and 16
108 bits, which is impossible in accordance with DW DMAC IP-core data book.
122 $ref: /schemas/types.yaml#/definitions/uint32-array
124 LLP-based multi-block transfer supported by hardware per
133 $ref: /schemas/types.yaml#/definitions/uint32-array
135 Maximum length of the burst transactions supported by the controller.
136 This property defines the upper limit of the run-time burst setting
137 (CTLx.SRC_MSIZE/CTLx.DST_MSIZE fields) so the allowed burst length
138 will be from 1 to max-burst-len words. It's an array property with one
139 cell per channel in the units determined by the value set in the
140 CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width).
144 enum: [4, 8, 16, 32, 64, 128, 256]
147 snps,dma-protection-control:
148 $ref: /schemas/types.yaml#/definitions/uint32
150 Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
151 indicates the following features: bit 0 - privileged mode,
152 bit 1 - DMA is bufferable, bit 2 - DMA is cacheable.
157 unevaluatedProperties: false
167 dma-controller@fc000000 {
168 compatible = "snps,dma-spear1340";
169 reg = <0xfc000000 0x1000>;
170 interrupt-parent = <&vic1>;
178 chan_allocation_order = <1>;
180 block_size = <0xfff>;
182 multi-block = <0 0 0 0 0 0 0 0>;
183 snps,max-burst-len = <16 16 4 4 4 4 4 4>;