Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright 2019 Texas Instruments Incorporated
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Texas Instruments J721E Display Subsystem
   9
  10 maintainers:
  11   - Jyri Sarha <jsarha@ti.com>
  12   - Tomi Valkeinen <tomi.valkeinen@ti.com>
  13
  14 description: |
  15   The J721E TI Keystone Display SubSystem with four output ports and
  16   four video planes. There is two full video planes and two "lite
  17   planes" without scaling support. The video ports can be connected to
  18   the SoC's DPI pins or to integrated display bridges on the SoC.
  19
  20 properties:
  21   compatible:
  22     const: ti,j721e-dss
  23
  24   reg:
  25     items:
  26       - description: common_m DSS Master common
  27       - description: common_s0 DSS Shared common 0
  28       - description: common_s1 DSS Shared common 1
  29       - description: common_s2 DSS Shared common 2
  30       - description: VIDL1 light video plane 1
  31       - description: VIDL2 light video plane 2
  32       - description: VID1 video plane 1
  33       - description: VID1 video plane 2
  34       - description: OVR1 overlay manager for vp1
  35       - description: OVR2 overlay manager for vp2
  36       - description: OVR3 overlay manager for vp3
  37       - description: OVR4 overlay manager for vp4
  38       - description: VP1 video port 1
  39       - description: VP2 video port 2
  40       - description: VP3 video port 3
  41       - description: VP4 video port 4
  42       - description: WB Write Back
  43
  44   reg-names:
  45     items:
  46       - const: common_m
  47       - const: common_s0
  48       - const: common_s1
  49       - const: common_s2
  50       - const: vidl1
  51       - const: vidl2
  52       - const: vid1
  53       - const: vid2
  54       - const: ovr1
  55       - const: ovr2
  56       - const: ovr3
  57       - const: ovr4
  58       - const: vp1
  59       - const: vp2
  60       - const: vp3
  61       - const: vp4
  62       - const: wb
  63
  64   clocks:
  65     items:
  66       - description: fck DSS functional clock
  67       - description: vp1 Video Port 1 pixel clock
  68       - description: vp2 Video Port 2 pixel clock
  69       - description: vp3 Video Port 3 pixel clock
  70       - description: vp4 Video Port 4 pixel clock
  71
  72   clock-names:
  73     items:
  74       - const: fck
  75       - const: vp1
  76       - const: vp2
  77       - const: vp3
  78       - const: vp4
  79
  80   assigned-clocks:
  81     minItems: 1
  82     maxItems: 5
  83
  84   assigned-clock-parents:
  85     minItems: 1
  86     maxItems: 5
  87
  88   interrupts:
  89     items:
  90       - description: common_m DSS Master common
  91       - description: common_s0 DSS Shared common 0
  92       - description: common_s1 DSS Shared common 1
  93       - description: common_s2 DSS Shared common 2
  94
  95   interrupt-names:
  96     items:
  97       - const: common_m
  98       - const: common_s0
  99       - const: common_s1
 100       - const: common_s2
 101
 102   power-domains:
 103     maxItems: 1
 104     description: phandle to the associated power domain
 105
 106   dma-coherent:
 107     type: boolean
 108
 109   ports:
 110     $ref: /schemas/graph.yaml#/properties/ports
 111
 112     properties:
 113       port@0:
 114         $ref: /schemas/graph.yaml#/properties/port
 115         description:
 116           The output port node form video port 1
 117
 118       port@1:
 119         $ref: /schemas/graph.yaml#/properties/port
 120         description:
 121           The output port node from video port 2
 122
 123       port@2:
 124         $ref: /schemas/graph.yaml#/properties/port
 125         description:
 126           The output port node from video port 3
 127
 128       port@3:
 129         $ref: /schemas/graph.yaml#/properties/port
 130         description:
 131           The output port node from video port 4
 132
 133   max-memory-bandwidth:
 134     $ref: /schemas/types.yaml#/definitions/uint32
 135     description:
 136       Input memory (from main memory to dispc) bandwidth limit in
 137       bytes per second
 138
 139 required:
 140   - compatible
 141   - reg
 142   - reg-names
 143   - clocks
 144   - clock-names
 145   - interrupts
 146   - interrupt-names
 147   - ports
 148
 149 additionalProperties: false
 150
 151 examples:
 152   - |
 153     #include <dt-bindings/interrupt-controller/arm-gic.h>
 154     #include <dt-bindings/interrupt-controller/irq.h>
 155     #include <dt-bindings/soc/ti,sci_pm_domain.h>
 156
 157     dss: dss@4a00000 {
 158             compatible = "ti,j721e-dss";
 159             reg =   <0x04a00000 0x10000>, /* common_m */
 160                     <0x04a10000 0x10000>, /* common_s0*/
 161                     <0x04b00000 0x10000>, /* common_s1*/
 162                     <0x04b10000 0x10000>, /* common_s2*/
 163                     <0x04a20000 0x10000>, /* vidl1 */
 164                     <0x04a30000 0x10000>, /* vidl2 */
 165                     <0x04a50000 0x10000>, /* vid1 */
 166                     <0x04a60000 0x10000>, /* vid2 */
 167                     <0x04a70000 0x10000>, /* ovr1 */
 168                     <0x04a90000 0x10000>, /* ovr2 */
 169                     <0x04ab0000 0x10000>, /* ovr3 */
 170                     <0x04ad0000 0x10000>, /* ovr4 */
 171                     <0x04a80000 0x10000>, /* vp1 */
 172                     <0x04aa0000 0x10000>, /* vp2 */
 173                     <0x04ac0000 0x10000>, /* vp3 */
 174                     <0x04ae0000 0x10000>, /* vp4 */
 175                     <0x04af0000 0x10000>; /* wb */
 176             reg-names = "common_m", "common_s0",
 177                     "common_s1", "common_s2",
 178                     "vidl1", "vidl2","vid1","vid2",
 179                     "ovr1", "ovr2", "ovr3", "ovr4",
 180                     "vp1", "vp2", "vp3", "vp4",
 181                     "wb";
 182             clocks =        <&k3_clks 152 0>,
 183                             <&k3_clks 152 1>,
 184                             <&k3_clks 152 4>,
 185                             <&k3_clks 152 9>,
 186                             <&k3_clks 152 13>;
 187             clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
 188             power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
 189             interrupts =    <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
 190                             <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
 191                             <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
 192                             <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 193             interrupt-names =       "common_m",
 194                                     "common_s0",
 195                                     "common_s1",
 196                                     "common_s2";
 197             ports {
 198                     #address-cells = <1>;
 199                     #size-cells = <0>;
 200                     port@0 {
 201                             reg = <0>;
 202
 203                             dpi_out_0: endpoint {
 204                                     remote-endpoint = <&dp_bridge_input>;
 205                             };
 206                     };
 207             };
 208     };