Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright 2019 Texas Instruments Incorporated
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Texas Instruments AM65x Display Subsystem
   9
  10 maintainers:
  11   - Jyri Sarha <jsarha@ti.com>
  12   - Tomi Valkeinen <tomi.valkeinen@ti.com>
  13
  14 description: |
  15   The AM65x TI Keystone Display SubSystem with two output ports and
  16   two video planes. The first video port supports OLDI and the second
  17   supports DPI format. The fist plane is full video plane with all
  18   features and the second is a "lite plane" without scaling support.
  19
  20 properties:
  21   compatible:
  22     const: ti,am65x-dss
  23
  24   reg:
  25     description:
  26       Addresses to each DSS memory region described in the SoC's TRM.
  27     items:
  28       - description: common DSS register area
  29       - description: VIDL1 light video plane
  30       - description: VID video plane
  31       - description: OVR1 overlay manager for vp1
  32       - description: OVR2 overlay manager for vp2
  33       - description: VP1 video port 1
  34       - description: VP2 video port 2
  35
  36   reg-names:
  37     items:
  38       - const: common
  39       - const: vidl1
  40       - const: vid
  41       - const: ovr1
  42       - const: ovr2
  43       - const: vp1
  44       - const: vp2
  45
  46   clocks:
  47     items:
  48       - description: fck DSS functional clock
  49       - description: vp1 Video Port 1 pixel clock
  50       - description: vp2 Video Port 2 pixel clock
  51
  52   clock-names:
  53     items:
  54       - const: fck
  55       - const: vp1
  56       - const: vp2
  57
  58   assigned-clocks:
  59     minItems: 1
  60     maxItems: 3
  61
  62   assigned-clock-parents:
  63     minItems: 1
  64     maxItems: 3
  65
  66   interrupts:
  67     maxItems: 1
  68
  69   power-domains:
  70     maxItems: 1
  71     description: phandle to the associated power domain
  72
  73   dma-coherent:
  74     type: boolean
  75
  76   ports:
  77     $ref: /schemas/graph.yaml#/properties/ports
  78
  79     properties:
  80       port@0:
  81         $ref: /schemas/graph.yaml#/properties/port
  82         description:
  83           The DSS OLDI output port node form video port 1
  84
  85       port@1:
  86         $ref: /schemas/graph.yaml#/properties/port
  87         description:
  88           The DSS DPI output port node from video port 2
  89
  90   ti,am65x-oldi-io-ctrl:
  91     $ref: "/schemas/types.yaml#/definitions/phandle"
  92     description:
  93       phandle to syscon device node mapping OLDI IO_CTRL registers.
  94       The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
  95       following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
  96       and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
  97       interface to work.
  98
  99   max-memory-bandwidth:
 100     $ref: /schemas/types.yaml#/definitions/uint32
 101     description:
 102       Input memory (from main memory to dispc) bandwidth limit in
 103       bytes per second
 104
 105 required:
 106   - compatible
 107   - reg
 108   - reg-names
 109   - clocks
 110   - clock-names
 111   - interrupts
 112   - ports
 113
 114 additionalProperties: false
 115
 116 examples:
 117   - |
 118     #include <dt-bindings/interrupt-controller/arm-gic.h>
 119     #include <dt-bindings/interrupt-controller/irq.h>
 120     #include <dt-bindings/soc/ti,sci_pm_domain.h>
 121
 122     dss: dss@4a00000 {
 123             compatible = "ti,am65x-dss";
 124             reg =   <0x04a00000 0x1000>, /* common */
 125                     <0x04a02000 0x1000>, /* vidl1 */
 126                     <0x04a06000 0x1000>, /* vid */
 127                     <0x04a07000 0x1000>, /* ovr1 */
 128                     <0x04a08000 0x1000>, /* ovr2 */
 129                     <0x04a0a000 0x1000>, /* vp1 */
 130                     <0x04a0b000 0x1000>; /* vp2 */
 131             reg-names = "common", "vidl1", "vid",
 132                     "ovr1", "ovr2", "vp1", "vp2";
 133             ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
 134             power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
 135             clocks =        <&k3_clks 67 1>,
 136                             <&k3_clks 216 1>,
 137                             <&k3_clks 67 2>;
 138             clock-names = "fck", "vp1", "vp2";
 139             interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
 140             ports {
 141                     #address-cells = <1>;
 142                     #size-cells = <0>;
 143                     port@0 {
 144                             reg = <0>;
 145                             oldi_out0: endpoint {
 146                                     remote-endpoint = <&lcd_in0>;
 147                             };
 148                     };
 149             };
 150     };