1 Allwinner A10 Display Pipeline
2 ==============================
4 The Allwinner A10 Display pipeline is composed of several components
5 that are going to be documented below:
10 The TV Encoder supports the composite and VGA output. It is one end of
14 - compatible: value should be "allwinner,sun4i-a10-tv-encoder".
15 - reg: base address and size of memory-mapped region
16 - clocks: the clocks driving the TV encoder
17 - resets: phandle to the reset controller driving the encoder
19 - ports: A ports node with endpoint definitions as defined in
20 Documentation/devicetree/bindings/media/video-interfaces.txt. The
21 first port should be the input endpoint.
26 The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
29 - compatible: value must be either:
30 * allwinner,sun5i-a13-tcon
31 * allwinner,sun6i-a31-tcon
32 * allwinner,sun6i-a31s-tcon
33 * allwinner,sun8i-a33-tcon
34 - reg: base address and size of memory-mapped region
35 - interrupts: interrupt associated to this IP
36 - clocks: phandles to the clocks feeding the TCON. Three are needed:
37 - 'ahb': the interface clocks
38 - 'tcon-ch0': The clock driving the TCON channel 0
39 - resets: phandles to the reset controllers driving the encoder
40 - "lcd": the reset line for the TCON channel 0
42 - clock-names: the clock names mentioned above
43 - reset-names: the reset names mentioned above
44 - clock-output-names: Name of the pixel clock created
46 - ports: A ports node with endpoint definitions as defined in
47 Documentation/devicetree/bindings/media/video-interfaces.txt. The
48 first port should be the input endpoint, the second one the output
50 The output may have multiple endpoints. The TCON has two channels,
51 usually with the first channel being used for the panels interfaces
52 (RGB, LVDS, etc.), and the second being used for the outputs that
53 require another controller (TV Encoder, HDMI, etc.). The endpoints
54 will take an extra property, allwinner,tcon-channel, to specify the
55 channel the endpoint is associated to. If that property is not
56 present, the endpoint number will be used as the channel number.
58 On SoCs other than the A33, there is one more clock required:
59 - 'tcon-ch1': The clock driving the TCON channel 1
64 The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
65 (A31, A23, A33), allows to dynamically adjust pixel
66 brightness/contrast based on histogram measurements for LCD content
67 adaptive backlight control.
71 - compatible: value must be one of:
72 * allwinner,sun8i-a33-drc
73 - reg: base address and size of the memory-mapped region.
74 - interrupts: interrupt associated to this IP
75 - clocks: phandles to the clocks feeding the DRC
76 * ahb: the DRC interface clock
77 * mod: the DRC module clock
78 * ram: the DRC DRAM clock
79 - clock-names: the clock names mentioned above
80 - resets: phandles to the reset line driving the DRC
82 - ports: A ports node with endpoint definitions as defined in
83 Documentation/devicetree/bindings/media/video-interfaces.txt. The
84 first port should be the input endpoints, the second one the outputs
86 Display Engine Backend
87 ----------------------
89 The display engine backend exposes layers and sprites to the
93 - compatible: value must be one of:
94 * allwinner,sun5i-a13-display-backend
95 * allwinner,sun6i-a31-display-backend
96 * allwinner,sun8i-a33-display-backend
97 - reg: base address and size of the memory-mapped region.
98 - clocks: phandles to the clocks feeding the frontend and backend
99 * ahb: the backend interface clock
100 * mod: the backend module clock
101 * ram: the backend DRAM clock
102 - clock-names: the clock names mentioned above
103 - resets: phandles to the reset controllers driving the backend
105 - ports: A ports node with endpoint definitions as defined in
106 Documentation/devicetree/bindings/media/video-interfaces.txt. The
107 first port should be the input endpoints, the second one the output
109 On the A33, some additional properties are required:
110 - reg needs to have an additional region corresponding to the SAT
111 - reg-names need to be set, with "be" and "sat"
112 - clocks and clock-names need to have a phandle to the SAT bus
113 clocks, whose name will be "sat"
114 - resets and reset-names need to have a phandle to the SAT bus
115 resets, whose name will be "sat"
117 Display Engine Frontend
118 -----------------------
120 The display engine frontend does formats conversion, scaling,
121 deinterlacing and color space conversion.
124 - compatible: value must be one of:
125 * allwinner,sun5i-a13-display-frontend
126 * allwinner,sun6i-a31-display-frontend
127 * allwinner,sun8i-a33-display-frontend
128 - reg: base address and size of the memory-mapped region.
129 - interrupts: interrupt associated to this IP
130 - clocks: phandles to the clocks feeding the frontend and backend
131 * ahb: the backend interface clock
132 * mod: the backend module clock
133 * ram: the backend DRAM clock
134 - clock-names: the clock names mentioned above
135 - resets: phandles to the reset controllers driving the backend
137 - ports: A ports node with endpoint definitions as defined in
138 Documentation/devicetree/bindings/media/video-interfaces.txt. The
139 first port should be the input endpoints, the second one the outputs
142 Display Engine Pipeline
143 -----------------------
145 The display engine pipeline (and its entry point, since it can be
146 either directly the backend or the frontend) is represented as an
150 - compatible: value must be one of:
151 * allwinner,sun5i-a13-display-engine
152 * allwinner,sun6i-a31-display-engine
153 * allwinner,sun6i-a31s-display-engine
154 * allwinner,sun8i-a33-display-engine
156 - allwinner,pipelines: list of phandle to the display engine
162 compatible = "olimex,lcd-olinuxino-43-ts";
163 #address-cells = <1>;
167 #address-cells = <1>;
170 panel_input: endpoint {
171 remote-endpoint = <&tcon0_out_panel>;
176 tve0: tv-encoder@01c0a000 {
177 compatible = "allwinner,sun4i-a10-tv-encoder";
178 reg = <0x01c0a000 0x1000>;
179 clocks = <&ahb_gates 34>;
180 resets = <&tcon_ch0_clk 0>;
183 #address-cells = <1>;
186 tve0_in_tcon0: endpoint@0 {
188 remote-endpoint = <&tcon0_out_tve0>;
193 tcon0: lcd-controller@1c0c000 {
194 compatible = "allwinner,sun5i-a13-tcon";
195 reg = <0x01c0c000 0x1000>;
197 resets = <&tcon_ch0_clk 1>;
199 clocks = <&ahb_gates 36>,
205 clock-output-names = "tcon-pixel-clock";
208 #address-cells = <1>;
212 #address-cells = <1>;
216 tcon0_in_be0: endpoint@0 {
218 remote-endpoint = <&be0_out_tcon0>;
223 #address-cells = <1>;
227 tcon0_out_panel: endpoint@0 {
229 remote-endpoint = <&panel_input>;
232 tcon0_out_tve0: endpoint@1 {
234 remote-endpoint = <&tve0_in_tcon0>;
240 fe0: display-frontend@1e00000 {
241 compatible = "allwinner,sun5i-a13-display-frontend";
242 reg = <0x01e00000 0x20000>;
244 clocks = <&ahb_gates 46>, <&de_fe_clk>,
246 clock-names = "ahb", "mod",
248 resets = <&de_fe_clk>;
251 #address-cells = <1>;
255 #address-cells = <1>;
259 fe0_out_be0: endpoint {
260 remote-endpoint = <&be0_in_fe0>;
266 be0: display-backend@1e60000 {
267 compatible = "allwinner,sun5i-a13-display-backend";
268 reg = <0x01e60000 0x10000>;
269 clocks = <&ahb_gates 44>, <&de_be_clk>,
271 clock-names = "ahb", "mod",
273 resets = <&de_be_clk>;
276 #address-cells = <1>;
280 #address-cells = <1>;
284 be0_in_fe0: endpoint@0 {
286 remote-endpoint = <&fe0_out_be0>;
291 #address-cells = <1>;
295 be0_out_tcon0: endpoint@0 {
297 remote-endpoint = <&tcon0_in_be0>;
304 compatible = "allwinner,sun5i-a13-display-engine";
305 allwinner,pipelines = <&fe0>;