Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
   8
   9 maintainers:
  10   - Inki Dae <inki.dae@samsung.com>
  11   - Joonyoung Shim <jy0922.shim@samsung.com>
  12   - Seung-Woo Kim <sw0312.kim@samsung.com>
  13   - Kyungmin Park <kyungmin.park@samsung.com>
  14   - Krzysztof Kozlowski <krzk@kernel.org>
  15
  16 description: |
  17   DECON (Display and Enhancement Controller) is the Display Controller for the
  18   Exynos7 series of SoCs which transfers the image data from a video memory
  19   buffer to an external LCD interface.
  20
  21 properties:
  22   compatible:
  23     const: samsung,exynos7-decon
  24
  25   clocks:
  26     minItems: 4
  27     maxItems: 4
  28
  29   clock-names:
  30     items:
  31       - const: pclk_decon0
  32       - const: aclk_decon0
  33       - const: decon0_eclk
  34       - const: decon0_vclk
  35
  36   display-timings:
  37     $ref: ../panel/display-timings.yaml#
  38
  39   i80-if-timings:
  40     type: object
  41     description: timing configuration for lcd i80 interface support
  42     properties:
  43       cs-setup:
  44         $ref: /schemas/types.yaml#/definitions/uint32
  45         description:
  46           Clock cycles for the active period of address signal is enabled until
  47           chip select is enabled.
  48         default: 0
  49
  50       wr-active:
  51         $ref: /schemas/types.yaml#/definitions/uint32
  52         description:
  53           Clock cycles for the active period of CS is enabled.
  54         default: 1
  55
  56       wr-hold:
  57         $ref: /schemas/types.yaml#/definitions/uint32
  58         description:
  59           Clock cycles for the active period of CS is disabled until write
  60           signal is disabled.
  61         default: 0
  62
  63       wr-setup:
  64         $ref: /schemas/types.yaml#/definitions/uint32
  65         description:
  66           Clock cycles for the active period of CS signal is enabled until
  67           write signal is enabled.
  68         default: 0
  69
  70   interrupts:
  71     items:
  72       - description: FIFO level
  73       - description: VSYNC
  74       - description: LCD system
  75
  76   interrupt-names:
  77     items:
  78       - const: fifo
  79       - const: vsync
  80       - const: lcd_sys
  81
  82   power-domains:
  83     maxItems: 1
  84
  85   reg:
  86     maxItems: 1
  87
  88 required:
  89   - compatible
  90   - clocks
  91   - clock-names
  92   - interrupts
  93   - interrupt-names
  94   - reg
  95
  96 additionalProperties: false
  97
  98 examples:
  99   - |
 100     #include <dt-bindings/clock/exynos7-clk.h>
 101     #include <dt-bindings/interrupt-controller/arm-gic.h>
 102
 103     display-controller@13930000 {
 104         compatible = "samsung,exynos7-decon";
 105         reg = <0x13930000 0x1000>;
 106         interrupt-names = "fifo", "vsync", "lcd_sys";
 107         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 108                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 109                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 110         clocks = <&clock_disp 100>, /* PCLK_DECON_INT */
 111                  <&clock_disp 101>, /* ACLK_DECON_INT */
 112                  <&clock_disp 102>, /* SCLK_DECON_INT_ECLK */
 113                  <&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */
 114         clock-names = "pclk_decon0",
 115                       "aclk_decon0",
 116                       "decon0_eclk",
 117                       "decon0_vclk";
 118         pinctrl-0 = <&lcd_clk &pwm1_out>;
 119         pinctrl-names = "default";
 120     };