Documentation/devicetree/bindings/display/rockchip/rockchip,rk3066-hdmi.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3066-hdmi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Rockchip rk3066 HDMI controller
   8
   9 maintainers:
  10   - Sandy Huang <hjc@rock-chips.com>
  11   - Heiko Stuebner <heiko@sntech.de>
  12
  13 properties:
  14   compatible:
  15     const: rockchip,rk3066-hdmi
  16
  17   reg:
  18     maxItems: 1
  19
  20   interrupts:
  21     maxItems: 1
  22
  23   clocks:
  24     maxItems: 1
  25
  26   clock-names:
  27     const: hclk
  28
  29   power-domains:
  30     maxItems: 1
  31
  32   rockchip,grf:
  33     $ref: /schemas/types.yaml#/definitions/phandle
  34     description:
  35       This soc uses GRF regs to switch the HDMI TX input between vop0 and vop1.
  36
  37   ports:
  38     $ref: /schemas/graph.yaml#/properties/ports
  39
  40     properties:
  41       port@0:
  42         $ref: /schemas/graph.yaml#/properties/port
  43         description:
  44           Port node with two endpoints, numbered 0 and 1,
  45           connected respectively to vop0 and vop1.
  46
  47       port@1:
  48         $ref: /schemas/graph.yaml#/properties/port
  49         description:
  50           Port node with one endpoint connected to a hdmi-connector node.
  51
  52     required:
  53       - port@0
  54       - port@1
  55
  56 required:
  57   - compatible
  58   - reg
  59   - interrupts
  60   - clocks
  61   - clock-names
  62   - pinctrl-0
  63   - pinctrl-names
  64   - power-domains
  65   - rockchip,grf
  66   - ports
  67
  68 additionalProperties: false
  69
  70 examples:
  71   - |
  72     #include <dt-bindings/clock/rk3066a-cru.h>
  73     #include <dt-bindings/interrupt-controller/arm-gic.h>
  74     #include <dt-bindings/pinctrl/rockchip.h>
  75     #include <dt-bindings/power/rk3066-power.h>
  76     hdmi: hdmi@10116000 {
  77       compatible = "rockchip,rk3066-hdmi";
  78       reg = <0x10116000 0x2000>;
  79       interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  80       clocks = <&cru HCLK_HDMI>;
  81       clock-names = "hclk";
  82       pinctrl-0 = <&hdmii2c_xfer>, <&hdmi_hpd>;
  83       pinctrl-names = "default";
  84       power-domains = <&power RK3066_PD_VIO>;
  85       rockchip,grf = <&grf>;
  86
  87       ports {
  88         #address-cells = <1>;
  89         #size-cells = <0>;
  90         hdmi_in: port@0 {
  91           reg = <0>;
  92           #address-cells = <1>;
  93           #size-cells = <0>;
  94           hdmi_in_vop0: endpoint@0 {
  95             reg = <0>;
  96             remote-endpoint = <&vop0_out_hdmi>;
  97           };
  98           hdmi_in_vop1: endpoint@1 {
  99             reg = <1>;
 100             remote-endpoint = <&vop1_out_hdmi>;
 101           };
 102         };
 103         hdmi_out: port@1 {
 104           reg = <1>;
 105           hdmi_out_con: endpoint {
 106             remote-endpoint = <&hdmi_con_in>;
 107           };
 108         };
 109       };
 110     };
 111
 112     pinctrl {
 113       hdmi {
 114         hdmi_hpd: hdmi-hpd {
 115           rockchip,pins = <0 RK_PA0 1 &pcfg_pull_default>;
 116         };
 117         hdmii2c_xfer: hdmii2c-xfer {
 118           rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>,
 119                           <0 RK_PA2 1 &pcfg_pull_none>;
 120         };
 121       };
 122     };