1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/renesas,du.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Display Unit (DU)
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the Display Unit embedded in the Renesas R-Car
14 Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,du-r8a7742 # for RZ/G1H compatible DU
20 - renesas,du-r8a7743 # for RZ/G1M compatible DU
21 - renesas,du-r8a7744 # for RZ/G1N compatible DU
22 - renesas,du-r8a7745 # for RZ/G1E compatible DU
23 - renesas,du-r8a77470 # for RZ/G1C compatible DU
24 - renesas,du-r8a774a1 # for RZ/G2M compatible DU
25 - renesas,du-r8a774b1 # for RZ/G2N compatible DU
26 - renesas,du-r8a774c0 # for RZ/G2E compatible DU
27 - renesas,du-r8a774e1 # for RZ/G2H compatible DU
28 - renesas,du-r8a7779 # for R-Car H1 compatible DU
29 - renesas,du-r8a7790 # for R-Car H2 compatible DU
30 - renesas,du-r8a7791 # for R-Car M2-W compatible DU
31 - renesas,du-r8a7792 # for R-Car V2H compatible DU
32 - renesas,du-r8a7793 # for R-Car M2-N compatible DU
33 - renesas,du-r8a7794 # for R-Car E2 compatible DU
34 - renesas,du-r8a7795 # for R-Car H3 compatible DU
35 - renesas,du-r8a7796 # for R-Car M3-W compatible DU
36 - renesas,du-r8a77961 # for R-Car M3-W+ compatible DU
37 - renesas,du-r8a77965 # for R-Car M3-N compatible DU
38 - renesas,du-r8a77970 # for R-Car V3M compatible DU
39 - renesas,du-r8a77980 # for R-Car V3H compatible DU
40 - renesas,du-r8a77990 # for R-Car E3 compatible DU
41 - renesas,du-r8a77995 # for R-Car D3 compatible DU
46 # See compatible-specific constraints below.
50 description: Interrupt specifiers, one per DU channel
58 $ref: /schemas/graph.yaml#/properties/ports
60 The connections to the DU output video ports are modeled using the OF
61 graph bindings specified in Documentation/devicetree/bindings/graph.txt.
62 The number of ports and their assignment are model-dependent. Each port
63 shall have a single endpoint.
67 $ref: /schemas/graph.yaml#/properties/port
68 unevaluatedProperties: false
74 unevaluatedProperties: false
77 $ref: "/schemas/types.yaml#/definitions/phandle-array"
79 A list of phandles to the CMM instances present in the SoC, one for each
83 $ref: "/schemas/types.yaml#/definitions/phandle-array"
85 A list of phandle and channel index tuples to the VSPs that handle the
86 memory interfaces for the DU channels. The phandle identifies the VSP
87 instance that serves the DU channel, and the channel index identifies
88 the LIF instance in that VSP.
102 const: renesas,du-r8a7779
109 - description: Functional clock
110 - description: DU_DOTCLKIN0 input clock
111 - description: DU_DOTCLKIN1 input clock
118 - pattern: '^dclkin\.[01]$'
119 - pattern: '^dclkin\.[01]$'
133 # port@2 is TCON, not supported yet
159 - description: Functional clock for DU0
160 - description: Functional clock for DU1
161 - description: DU_DOTCLKIN0 input clock
162 - description: DU_DOTCLKIN1 input clock
170 - pattern: '^dclkin\.[01]$'
171 - pattern: '^dclkin\.[01]$'
189 # port@2 is TCON, not supported yet
216 - description: Functional clock for DU0
217 - description: Functional clock for DU1
218 - description: DU_DOTCLKIN0 input clock
219 - description: DU_DOTCLKIN1 input clock
227 - pattern: '^dclkin\.[01]$'
228 - pattern: '^dclkin\.[01]$'
271 - description: Functional clock for DU0
272 - description: Functional clock for DU1
273 - description: DU_DOTCLKIN0 input clock
274 - description: DU_DOTCLKIN1 input clock
282 - pattern: '^dclkin\.[01]$'
283 - pattern: '^dclkin\.[01]$'
301 # port@2 is TCON, not supported yet
320 - renesas,du-r8a77470
327 - description: Functional clock for DU0
328 - description: Functional clock for DU1
329 - description: DU_DOTCLKIN0 input clock
330 - description: DU_DOTCLKIN1 input clock
338 - pattern: '^dclkin\.[01]$'
339 - pattern: '^dclkin\.[01]$'
359 # port@3 is DVENC, not supported yet
386 - description: Functional clock for DU0
387 - description: Functional clock for DU1
388 - description: Functional clock for DU2
389 - description: DU_DOTCLKIN0 input clock
390 - description: DU_DOTCLKIN1 input clock
391 - description: DU_DOTCLKIN2 input clock
400 - pattern: '^dclkin\.[012]$'
401 - pattern: '^dclkin\.[012]$'
402 - pattern: '^dclkin\.[012]$'
422 # port@3 is TCON, not supported yet
448 - description: Functional clock for DU0
449 - description: Functional clock for DU1
450 - description: Functional clock for DU2
451 - description: Functional clock for DU4
452 - description: DU_DOTCLKIN0 input clock
453 - description: DU_DOTCLKIN1 input clock
454 - description: DU_DOTCLKIN2 input clock
455 - description: DU_DOTCLKIN3 input clock
465 - pattern: '^dclkin\.[0123]$'
466 - pattern: '^dclkin\.[0123]$'
467 - pattern: '^dclkin\.[0123]$'
468 - pattern: '^dclkin\.[0123]$'
516 - renesas,du-r8a774a1
518 - renesas,du-r8a77961
525 - description: Functional clock for DU0
526 - description: Functional clock for DU1
527 - description: Functional clock for DU2
528 - description: DU_DOTCLKIN0 input clock
529 - description: DU_DOTCLKIN1 input clock
530 - description: DU_DOTCLKIN2 input clock
539 - pattern: '^dclkin\.[012]$'
540 - pattern: '^dclkin\.[012]$'
541 - pattern: '^dclkin\.[012]$'
587 - renesas,du-r8a774b1
588 - renesas,du-r8a774e1
589 - renesas,du-r8a77965
596 - description: Functional clock for DU0
597 - description: Functional clock for DU1
598 - description: Functional clock for DU3
599 - description: DU_DOTCLKIN0 input clock
600 - description: DU_DOTCLKIN1 input clock
601 - description: DU_DOTCLKIN3 input clock
610 - pattern: '^dclkin\.[013]$'
611 - pattern: '^dclkin\.[013]$'
612 - pattern: '^dclkin\.[013]$'
658 - renesas,du-r8a77970
659 - renesas,du-r8a77980
666 - description: Functional clock for DU0
667 - description: DU_DOTCLKIN0 input clock
714 - renesas,du-r8a774c0
715 - renesas,du-r8a77990
716 - renesas,du-r8a77995
723 - description: Functional clock for DU0
724 - description: Functional clock for DU1
725 - description: DU_DOTCLKIN0 input clock
726 - description: DU_DOTCLKIN1 input clock
734 - pattern: '^dclkin\.[01]$'
735 - pattern: '^dclkin\.[01]$'
755 # port@3 is TCON, not supported yet
776 additionalProperties: false
781 #include <dt-bindings/clock/renesas-cpg-mssr.h>
782 #include <dt-bindings/interrupt-controller/arm-gic.h>
785 compatible = "renesas,du-r8a7795";
786 reg = <0xfeb00000 0x80000>;
787 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&cpg CPG_MOD 724>,
795 clock-names = "du.0", "du.1", "du.2", "du.3";
796 resets = <&cpg 724>, <&cpg 722>;
797 reset-names = "du.0", "du.2";
799 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
800 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
803 #address-cells = <1>;
809 remote-endpoint = <&adv7123_in>;
815 remote-endpoint = <&dw_hdmi0_in>;
821 remote-endpoint = <&dw_hdmi1_in>;
827 remote-endpoint = <&lvds0_in>;