1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/renesas,du.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Display Unit (DU)
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 These DT bindings describe the Display Unit embedded in the Renesas R-Car
14 Gen1, R-Car Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,du-r8a7742 # for RZ/G1H compatible DU
20 - renesas,du-r8a7743 # for RZ/G1M compatible DU
21 - renesas,du-r8a7744 # for RZ/G1N compatible DU
22 - renesas,du-r8a7745 # for RZ/G1E compatible DU
23 - renesas,du-r8a77470 # for RZ/G1C compatible DU
24 - renesas,du-r8a774a1 # for RZ/G2M compatible DU
25 - renesas,du-r8a774b1 # for RZ/G2N compatible DU
26 - renesas,du-r8a774c0 # for RZ/G2E compatible DU
27 - renesas,du-r8a774e1 # for RZ/G2H compatible DU
28 - renesas,du-r8a7779 # for R-Car H1 compatible DU
29 - renesas,du-r8a7790 # for R-Car H2 compatible DU
30 - renesas,du-r8a7791 # for R-Car M2-W compatible DU
31 - renesas,du-r8a7792 # for R-Car V2H compatible DU
32 - renesas,du-r8a7793 # for R-Car M2-N compatible DU
33 - renesas,du-r8a7794 # for R-Car E2 compatible DU
34 - renesas,du-r8a7795 # for R-Car H3 compatible DU
35 - renesas,du-r8a7796 # for R-Car M3-W compatible DU
36 - renesas,du-r8a77961 # for R-Car M3-W+ compatible DU
37 - renesas,du-r8a77965 # for R-Car M3-N compatible DU
38 - renesas,du-r8a77970 # for R-Car V3M compatible DU
39 - renesas,du-r8a77980 # for R-Car V3H compatible DU
40 - renesas,du-r8a77990 # for R-Car E3 compatible DU
41 - renesas,du-r8a77995 # for R-Car D3 compatible DU
42 - renesas,du-r8a779a0 # for R-Car V3U compatible DU
47 # See compatible-specific constraints below.
51 description: Interrupt specifiers, one per DU channel
59 $ref: /schemas/graph.yaml#/properties/ports
61 The connections to the DU output video ports are modeled using the OF
62 graph bindings specified in Documentation/devicetree/bindings/graph.txt.
63 The number of ports and their assignment are model-dependent. Each port
64 shall have a single endpoint.
68 $ref: /schemas/graph.yaml#/properties/port
69 unevaluatedProperties: false
75 unevaluatedProperties: false
78 $ref: "/schemas/types.yaml#/definitions/phandle-array"
82 A list of phandles to the CMM instances present in the SoC, one for each
86 $ref: "/schemas/types.yaml#/definitions/phandle-array"
89 - description: phandle to VSP instance that serves the DU channel
90 - description: Channel index identifying the LIF instance in that VSP
92 A list of phandle and channel index tuples to the VSPs that handle the
93 memory interfaces for the DU channels.
107 const: renesas,du-r8a7779
113 - description: Functional clock
114 - description: DU_DOTCLKIN0 input clock
115 - description: DU_DOTCLKIN1 input clock
121 - pattern: '^dclkin\.[01]$'
122 - pattern: '^dclkin\.[01]$'
136 # port@2 is TCON, not supported yet
161 - description: Functional clock for DU0
162 - description: Functional clock for DU1
163 - description: DU_DOTCLKIN0 input clock
164 - description: DU_DOTCLKIN1 input clock
171 - pattern: '^dclkin\.[01]$'
172 - pattern: '^dclkin\.[01]$'
190 # port@2 is TCON, not supported yet
216 - description: Functional clock for DU0
217 - description: Functional clock for DU1
218 - description: DU_DOTCLKIN0 input clock
219 - description: DU_DOTCLKIN1 input clock
226 - pattern: '^dclkin\.[01]$'
227 - pattern: '^dclkin\.[01]$'
269 - description: Functional clock for DU0
270 - description: Functional clock for DU1
271 - description: DU_DOTCLKIN0 input clock
272 - description: DU_DOTCLKIN1 input clock
279 - pattern: '^dclkin\.[01]$'
280 - pattern: '^dclkin\.[01]$'
298 # port@2 is TCON, not supported yet
317 - renesas,du-r8a77470
323 - description: Functional clock for DU0
324 - description: Functional clock for DU1
325 - description: DU_DOTCLKIN0 input clock
326 - description: DU_DOTCLKIN1 input clock
333 - pattern: '^dclkin\.[01]$'
334 - pattern: '^dclkin\.[01]$'
354 # port@3 is DVENC, not supported yet
380 - description: Functional clock for DU0
381 - description: Functional clock for DU1
382 - description: Functional clock for DU2
383 - description: DU_DOTCLKIN0 input clock
384 - description: DU_DOTCLKIN1 input clock
385 - description: DU_DOTCLKIN2 input clock
393 - pattern: '^dclkin\.[012]$'
394 - pattern: '^dclkin\.[012]$'
395 - pattern: '^dclkin\.[012]$'
415 # port@3 is TCON, not supported yet
440 - description: Functional clock for DU0
441 - description: Functional clock for DU1
442 - description: Functional clock for DU2
443 - description: Functional clock for DU4
444 - description: DU_DOTCLKIN0 input clock
445 - description: DU_DOTCLKIN1 input clock
446 - description: DU_DOTCLKIN2 input clock
447 - description: DU_DOTCLKIN3 input clock
456 - pattern: '^dclkin\.[0123]$'
457 - pattern: '^dclkin\.[0123]$'
458 - pattern: '^dclkin\.[0123]$'
459 - pattern: '^dclkin\.[0123]$'
507 - renesas,du-r8a774a1
509 - renesas,du-r8a77961
515 - description: Functional clock for DU0
516 - description: Functional clock for DU1
517 - description: Functional clock for DU2
518 - description: DU_DOTCLKIN0 input clock
519 - description: DU_DOTCLKIN1 input clock
520 - description: DU_DOTCLKIN2 input clock
528 - pattern: '^dclkin\.[012]$'
529 - pattern: '^dclkin\.[012]$'
530 - pattern: '^dclkin\.[012]$'
576 - renesas,du-r8a774b1
577 - renesas,du-r8a774e1
578 - renesas,du-r8a77965
584 - description: Functional clock for DU0
585 - description: Functional clock for DU1
586 - description: Functional clock for DU3
587 - description: DU_DOTCLKIN0 input clock
588 - description: DU_DOTCLKIN1 input clock
589 - description: DU_DOTCLKIN3 input clock
597 - pattern: '^dclkin\.[013]$'
598 - pattern: '^dclkin\.[013]$'
599 - pattern: '^dclkin\.[013]$'
645 - renesas,du-r8a77970
646 - renesas,du-r8a77980
652 - description: Functional clock for DU0
653 - description: DU_DOTCLKIN0 input clock
699 - renesas,du-r8a774c0
700 - renesas,du-r8a77990
701 - renesas,du-r8a77995
707 - description: Functional clock for DU0
708 - description: Functional clock for DU1
709 - description: DU_DOTCLKIN0 input clock
710 - description: DU_DOTCLKIN1 input clock
717 - pattern: '^dclkin\.[01]$'
718 - pattern: '^dclkin\.[01]$'
738 # port@3 is TCON, not supported yet
764 - renesas,du-r8a779a0
769 - description: Functional clock
808 additionalProperties: false
813 #include <dt-bindings/clock/renesas-cpg-mssr.h>
814 #include <dt-bindings/interrupt-controller/arm-gic.h>
817 compatible = "renesas,du-r8a7795";
818 reg = <0xfeb00000 0x80000>;
819 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&cpg CPG_MOD 724>,
827 clock-names = "du.0", "du.1", "du.2", "du.3";
828 resets = <&cpg 724>, <&cpg 722>;
829 reset-names = "du.0", "du.2";
831 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
832 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
835 #address-cells = <1>;
841 remote-endpoint = <&adv7123_in>;
847 remote-endpoint = <&dw_hdmi0_in>;
853 remote-endpoint = <&dw_hdmi1_in>;
859 remote-endpoint = <&lvds0_in>;