Documentation/devicetree/bindings/display/renesas,du.txt

   1 * Renesas R-Car Display Unit (DU)
   2
   3 Required Properties:
   4
   5   - compatible: must be one of the following.
   6     - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
   7     - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
   8     - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU
   9     - "renesas,du-r8a7792" for R8A7792 (R-Car V2H) compatible DU
  10     - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
  11     - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
  12     - "renesas,du-r8a7795" for R8A7795 (R-Car H3) compatible DU
  13     - "renesas,du-r8a7796" for R8A7796 (R-Car M3-W) compatible DU
  14
  15   - reg: A list of base address and length of each memory resource, one for
  16     each entry in the reg-names property.
  17   - reg-names: Name of the memory resources. The DU requires one memory
  18     resource for the DU core (named "du") and one memory resource for each
  19     LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
  20     index).
  21
  22   - interrupt-parent: phandle of the parent interrupt controller.
  23   - interrupts: Interrupt specifiers for the DU interrupts.
  24
  25   - clocks: A list of phandles + clock-specifier pairs, one for each entry in
  26     the clock-names property.
  27   - clock-names: Name of the clocks. This property is model-dependent.
  28     - R8A7779 uses a single functional clock. The clock doesn't need to be
  29       named.
  30     - R8A779[0123456] use one functional clock per channel and one clock per
  31       LVDS encoder (if available). The functional clocks must be named "du.x"
  32       with "x" being the channel numerical index. The LVDS clocks must be
  33       named "lvds.x" with "x" being the LVDS encoder numerical index.
  34     - In addition to the functional and encoder clocks, all DU versions also
  35       support externally supplied pixel clocks. Those clocks are optional.
  36       When supplied they must be named "dclkin.x" with "x" being the input
  37       clock numerical index.
  38
  39   - vsps: A list of phandle and channel index tuples to the VSPs that handle
  40     the memory interfaces for the DU channels. The phandle identifies the VSP
  41     instance that serves the DU channel, and the channel index identifies the
  42     LIF instance in that VSP.
  43
  44 Required nodes:
  45
  46 The connections to the DU output video ports are modeled using the OF graph
  47 bindings specified in Documentation/devicetree/bindings/graph.txt.
  48
  49 The following table lists for each supported model the port number
  50 corresponding to each DU output.
  51
  52                 Port 0          Port1           Port2           Port3
  53 -----------------------------------------------------------------------------
  54  R8A7779 (H1)   DPAD 0          DPAD 1          -               -
  55  R8A7790 (H2)   DPAD            LVDS 0          LVDS 1          -
  56  R8A7791 (M2-W) DPAD            LVDS 0          -               -
  57  R8A7792 (V2H)  DPAD 0          DPAD 1          -               -
  58  R8A7793 (M2-N) DPAD            LVDS 0          -               -
  59  R8A7794 (E2)   DPAD 0          DPAD 1          -               -
  60  R8A7795 (H3)   DPAD            HDMI 0          HDMI 1          LVDS
  61  R8A7796 (M3-W) DPAD            HDMI            LVDS            -
  62
  63
  64 Example: R8A7795 (R-Car H3) ES2.0 DU
  65
  66         du: display@feb00000 {
  67                 compatible = "renesas,du-r8a7795";
  68                 reg = <0 0xfeb00000 0 0x80000>,
  69                       <0 0xfeb90000 0 0x14>;
  70                 reg-names = "du", "lvds.0";
  71                 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
  72                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
  73                              <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
  75                 clocks = <&cpg CPG_MOD 724>,
  76                          <&cpg CPG_MOD 723>,
  77                          <&cpg CPG_MOD 722>,
  78                          <&cpg CPG_MOD 721>,
  79                          <&cpg CPG_MOD 727>;
  80                 clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
  81                 vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, <&vspd0 1>;
  82
  83                 ports {
  84                         #address-cells = <1>;
  85                         #size-cells = <0>;
  86
  87                         port@0 {
  88                                 reg = <0>;
  89                                 du_out_rgb: endpoint {
  90                                 };
  91                         };
  92                         port@1 {
  93                                 reg = <1>;
  94                                 du_out_hdmi0: endpoint {
  95                                         remote-endpoint = <&dw_hdmi0_in>;
  96                                 };
  97                         };
  98                         port@2 {
  99                                 reg = <2>;
 100                                 du_out_hdmi1: endpoint {
 101                                         remote-endpoint = <&dw_hdmi1_in>;
 102                                 };
 103                         };
 104                         port@3 {
 105                                 reg = <3>;
 106                                 du_out_lvds0: endpoint {
 107                                 };
 108                         };
 109                 };
 110         };