1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: panel timing bindings
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
14 There are different ways of describing the timing data of a panel. The
15 devicetree representation corresponds to the one commonly found in datasheets
18 The parameters are defined as seen in the following illustration.
20 +----------+-------------------------------------+----------+-------+
22 | | |vback_porch | | |
24 +----------#######################################----------+-------+
27 | hback # | # hfront | hsync |
28 | porch # | hactive # porch | len |
29 |<-------->#<-------+--------------------------->#<-------->|<----->|
34 +----------#######################################----------+-------+
36 | | |vfront_porch | | |
38 +----------+-------------------------------------+----------+-------+
42 +----------+-------------------------------------+----------+-------+
45 The following is the panel timings shown with time on the x-axis.
46 This matches the timing diagrams often found in data sheets.
48 Active Front Sync Back
50 <-----------------------><----------------><-------------><-------------->
51 //////////////////////|
52 ////////////////////// |
53 ////////////////////// |.................. ................
56 Timing can be specified either as a typical value or as a tuple
57 of min, typ, max values.
62 description: Panel clock in Hz
65 $ref: /schemas/types.yaml#/definitions/uint32
66 description: Horizontal panel resolution in pixels
69 $ref: /schemas/types.yaml#/definitions/uint32
70 description: Vertical panel resolution in pixels
73 description: Horizontal front porch panel timing
74 $ref: /schemas/types.yaml#/definitions/uint32-array
78 description: typical number of pixels
82 description: min, typ, max number of pixels
85 description: Horizontal back porch timing
86 $ref: /schemas/types.yaml#/definitions/uint32-array
90 description: typical number of pixels
94 description: min, typ, max number of pixels
97 description: Horizontal sync length panel timing
98 $ref: /schemas/types.yaml#/definitions/uint32-array
102 description: typical number of pixels
106 description: min, typ, max number of pixels
109 description: Vertical front porch panel timing
110 $ref: /schemas/types.yaml#/definitions/uint32-array
114 description: typical number of lines
118 description: min, typ, max number of lines
121 description: Vertical back porch panel timing
122 $ref: /schemas/types.yaml#/definitions/uint32-array
126 description: typical number of lines
130 description: min, typ, max number of lines
133 description: Vertical sync length panel timing
134 $ref: /schemas/types.yaml#/definitions/uint32-array
138 description: typical number of lines
142 description: min, typ, max number of lines
146 Horizontal sync pulse.
147 0 selects active low, 1 selects active high.
148 If omitted then it is not used by the hardware
149 $ref: /schemas/types.yaml#/definitions/uint32
155 0 selects active low, 1 selects active high.
156 If omitted then it is not used by the hardware
157 $ref: /schemas/types.yaml#/definitions/uint32
163 0 selects active low, 1 selects active high.
164 If omitted then it is not used by the hardware
165 $ref: /schemas/types.yaml#/definitions/uint32
170 Data driving on rising or falling edge.
171 Use 0 to drive pixel data on falling edge and
172 sample data on rising edge.
173 Use 1 to drive pixel data on rising edge and
174 sample data on falling edge
175 $ref: /schemas/types.yaml#/definitions/uint32
180 Drive sync on rising or sample sync on falling edge.
181 If not specified then the setup is as specified by pixelclk-active.
182 Use 0 to drive sync on falling edge and
183 sample sync on rising edge of pixel clock.
184 Use 1 to drive sync on rising edge and
185 sample sync on falling edge of pixel clock
186 $ref: /schemas/types.yaml#/definitions/uint32
191 description: Enable interlaced mode
195 description: Enable double scan mode
199 description: Enable double clock mode
212 additionalProperties: false