1 * Freescale MXS LCD Interface (LCDIF)
6 - compatible: Should be "fsl,imx23-lcdif" for i.MX23.
7 Should be "fsl,imx28-lcdif" for i.MX28.
8 Should be "fsl,imx6sx-lcdif" for i.MX6SX.
9 - reg: Address and length of the register set for LCDIF
10 - interrupts: Should contain LCDIF interrupt
11 - clocks: A list of phandle + clock-specifier pairs, one for each
12 entry in 'clock-names'.
13 - clock-names: A list of clock names. For MXSFB it should contain:
14 - "pix" for the LCDIF block clock
15 - (MX6SX-only) "axi", "disp_axi" for the bus interface clock
18 - port: The connection to an encoder chip.
22 lcdif1: display-controller@2220000 {
23 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
24 reg = <0x02220000 0x4000>;
25 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
26 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
27 <&clks IMX6SX_CLK_LCDIF_APB>,
28 <&clks IMX6SX_CLK_DISPLAY_AXI>;
29 clock-names = "pix", "axi", "disp_axi";
32 parallel_out: endpoint {
33 remote-endpoint = <&panel_in_parallel>;
41 - compatible: Should be "fsl,imx23-lcdif" for i.MX23.
42 Should be "fsl,imx28-lcdif" for i.MX28.
43 - reg: Address and length of the register set for LCDIF
44 - interrupts: Should contain LCDIF interrupts
45 - display: phandle to display node (see below for details)
50 - bits-per-pixel: <16> for RGB565, <32> for RGB888/666.
51 - bus-width: number of data lines. Could be <8>, <16>, <18> or <24>.
54 - display-timings: Refer to binding doc display-timing.txt for details.
59 compatible = "fsl,imx28-lcdif";
60 reg = <0x80030000 2000>;
64 bits-per-pixel = <32>;
68 native-mode = <&timing0>;
70 clock-frequency = <33500000>;
82 pixelclk-active = <0>;