Documentation/devicetree/bindings/display/msm/hdmi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4
   5 $id: http://devicetree.org/schemas/display/msm/hdmi.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: Qualcomm Adreno/Snapdragon HDMI output
   9
  10 maintainers:
  11   - Rob Clark <robdclark@gmail.com>
  12
  13 properties:
  14   compatible:
  15     enum:
  16       - qcom,hdmi-tx-8084
  17       - qcom,hdmi-tx-8660
  18       - qcom,hdmi-tx-8960
  19       - qcom,hdmi-tx-8974
  20       - qcom,hdmi-tx-8994
  21       - qcom,hdmi-tx-8996
  22
  23   clocks:
  24     minItems: 1
  25     maxItems: 5
  26
  27   clock-names:
  28     minItems: 1
  29     maxItems: 5
  30
  31   reg:
  32     minItems: 1
  33     maxItems: 3
  34
  35   reg-names:
  36     minItems: 1
  37     items:
  38       - const: core_physical
  39       - const: qfprom_physical
  40       - const: hdcp_physical
  41
  42   interrupts:
  43     maxItems: 1
  44
  45   phys:
  46     maxItems: 1
  47
  48   phy-names:
  49     enum:
  50       - hdmi_phy
  51       - hdmi-phy
  52     deprecated: true
  53
  54   core-vdda-supply:
  55     description: phandle to VDDA supply regulator
  56
  57   hdmi-mux-supply:
  58     description: phandle to mux regulator
  59     deprecated: true
  60
  61   core-vcc-supply:
  62     description: phandle to VCC supply regulator
  63
  64   hpd-gpios:
  65     maxItems: 1
  66     description: hpd pin
  67
  68   qcom,hdmi-tx-mux-en-gpios:
  69     maxItems: 1
  70     deprecated: true
  71     description: HDMI mux enable pin
  72
  73   qcom,hdmi-tx-mux-sel-gpios:
  74     maxItems: 1
  75     deprecated: true
  76     description: HDMI mux select pin
  77
  78   qcom,hdmi-tx-mux-lpm-gpios:
  79     maxItems: 1
  80     deprecated: true
  81     description: HDMI mux lpm pin
  82
  83   '#sound-dai-cells':
  84     const: 1
  85
  86   ports:
  87     type: object
  88     $ref: /schemas/graph.yaml#/properties/ports
  89     properties:
  90       port@0:
  91         $ref: /schemas/graph.yaml#/$defs/port-base
  92         description: |
  93           Input endpoints of the controller.
  94
  95       port@1:
  96         $ref: /schemas/graph.yaml#/$defs/port-base
  97         description: |
  98           Output endpoints of the controller.
  99
 100     required:
 101       - port@0
 102
 103 required:
 104   - compatible
 105   - clocks
 106   - clock-names
 107   - reg
 108   - reg-names
 109   - interrupts
 110   - phys
 111
 112 allOf:
 113   - if:
 114       properties:
 115         compatible:
 116           contains:
 117             enum:
 118               - qcom,hdmi-tx-8960
 119               - qcom,hdmi-tx-8660
 120     then:
 121       properties:
 122         clocks:
 123           minItems: 3
 124           maxItems: 3
 125         clock-names:
 126           items:
 127             - const: core
 128             - const: master_iface
 129             - const: slave_iface
 130         core-vcc-supplies: false
 131
 132   - if:
 133       properties:
 134         compatible:
 135           contains:
 136             enum:
 137               - qcom,hdmi-tx-8974
 138               - qcom,hdmi-tx-8084
 139               - qcom,hdmi-tx-8994
 140               - qcom,hdmi-tx-8996
 141     then:
 142       properties:
 143         clocks:
 144           minItems: 5
 145         clock-names:
 146           items:
 147             - const: mdp_core
 148             - const: iface
 149             - const: core
 150             - const: alt_iface
 151             - const: extp
 152         hdmi-mux-supplies: false
 153
 154 additionalProperties: false
 155
 156 examples:
 157   - |
 158     #include <dt-bindings/gpio/gpio.h>
 159     #include <dt-bindings/interrupt-controller/irq.h>
 160     #include <dt-bindings/interrupt-controller/arm-gic.h>
 161     hdmi: hdmi@4a00000 {
 162       compatible = "qcom,hdmi-tx-8960";
 163       reg-names = "core_physical";
 164       reg = <0x04a00000 0x2f0>;
 165       interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 166       clock-names = "core",
 167                     "master_iface",
 168                     "slave_iface";
 169       clocks = <&clk 61>,
 170                <&clk 72>,
 171                <&clk 98>;
 172       hpd-gpios = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
 173       core-vdda-supply = <&pm8921_hdmi_mvs>;
 174       hdmi-mux-supply = <&ext_3p3v>;
 175       pinctrl-names = "default", "sleep";
 176       pinctrl-0 = <&hpd_active  &ddc_active  &cec_active>;
 177       pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
 178
 179       phys = <&hdmi_phy>;
 180     };
 181   - |
 182     #include <dt-bindings/clock/qcom,gcc-msm8996.h>
 183     #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
 184     #include <dt-bindings/gpio/gpio.h>
 185     #include <dt-bindings/interrupt-controller/irq.h>
 186     #include <dt-bindings/interrupt-controller/arm-gic.h>
 187     hdmi@9a0000 {
 188       compatible = "qcom,hdmi-tx-8996";
 189       reg = <0x009a0000 0x50c>,
 190             <0x00070000 0x6158>,
 191             <0x009e0000 0xfff>;
 192       reg-names = "core_physical",
 193                   "qfprom_physical",
 194                   "hdcp_physical";
 195
 196       interrupt-parent = <&mdss>;
 197       interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 198
 199       clocks = <&mmcc MDSS_MDP_CLK>,
 200                <&mmcc MDSS_AHB_CLK>,
 201                <&mmcc MDSS_HDMI_CLK>,
 202                <&mmcc MDSS_HDMI_AHB_CLK>,
 203                <&mmcc MDSS_EXTPCLK_CLK>;
 204       clock-names = "mdp_core",
 205                     "iface",
 206                     "core",
 207                     "alt_iface",
 208                     "extp";
 209
 210       phys = <&hdmi_phy>;
 211       #sound-dai-cells = <1>;
 212
 213       pinctrl-names = "default", "sleep";
 214       pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
 215       pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
 216
 217       core-vdda-supply = <&vreg_l12a_1p8>;
 218       core-vcc-supply = <&vreg_s4a_1p8>;
 219
 220       ports {
 221         #address-cells = <1>;
 222         #size-cells = <0>;
 223
 224         port@0 {
 225           reg = <0>;
 226           endpoint {
 227             remote-endpoint = <&mdp5_intf3_out>;
 228           };
 229         };
 230       };
 231     };
 232 ...