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[releases.git] / Documentation / devicetree / bindings / display / msm / dsi-phy-28nm.yaml
1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Qualcomm Display DSI 28nm PHY
8
9 maintainers:
10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12 allOf:
13   - $ref: dsi-phy-common.yaml#
14
15 properties:
16   compatible:
17     enum:
18       - qcom,dsi-phy-28nm-hpm
19       - qcom,dsi-phy-28nm-lp
20       - qcom,dsi-phy-28nm-8960
21
22   reg:
23     items:
24       - description: dsi pll register set
25       - description: dsi phy register set
26       - description: dsi phy regulator register set
27
28   reg-names:
29     items:
30       - const: dsi_pll
31       - const: dsi_phy
32       - const: dsi_phy_regulator
33
34   vddio-supply:
35     description: Phandle to vdd-io regulator device node.
36
37   qcom,dsi-phy-regulator-ldo-mode:
38     type: boolean
39     description: Indicates if the LDO mode PHY regulator is wanted.
40
41 required:
42   - compatible
43   - reg
44   - reg-names
45   - vddio-supply
46
47 unevaluatedProperties: false
48
49 examples:
50   - |
51      #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
52      #include <dt-bindings/clock/qcom,rpmh.h>
53
54      dsi-phy@fd922a00 {
55          compatible = "qcom,dsi-phy-28nm-lp";
56          reg = <0xfd922a00 0xd4>,
57                <0xfd922b00 0x2b0>,
58                <0xfd922d80 0x7b>;
59          reg-names = "dsi_pll",
60                      "dsi_phy",
61                      "dsi_phy_regulator";
62
63          #clock-cells = <1>;
64          #phy-cells = <0>;
65
66          vddio-supply = <&vddio_reg>;
67
68          clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
69                   <&rpmhcc RPMH_CXO_CLK>;
70          clock-names = "iface", "ref";
71      };
72 ...