Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display DSI controller
   8
   9 maintainers:
  10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
  11
  12 allOf:
  13   - $ref: "../dsi-controller.yaml#"
  14
  15 properties:
  16   compatible:
  17     enum:
  18       - qcom,mdss-dsi-ctrl
  19       - qcom,dsi-ctrl-6g-qcm2290
  20
  21   reg:
  22     maxItems: 1
  23
  24   reg-names:
  25     const: dsi_ctrl
  26
  27   interrupts:
  28     maxItems: 1
  29
  30   clocks:
  31     items:
  32       - description: Display byte clock
  33       - description: Display byte interface clock
  34       - description: Display pixel clock
  35       - description: Display core clock
  36       - description: Display AHB clock
  37       - description: Display AXI clock
  38
  39   clock-names:
  40     items:
  41       - const: byte
  42       - const: byte_intf
  43       - const: pixel
  44       - const: core
  45       - const: iface
  46       - const: bus
  47
  48   phys:
  49     maxItems: 1
  50
  51   phy-names:
  52     const: dsi
  53
  54   "#address-cells": true
  55
  56   "#size-cells": true
  57
  58   syscon-sfpb:
  59     description: A phandle to mmss_sfpb syscon node (only for DSIv2).
  60     $ref: "/schemas/types.yaml#/definitions/phandle"
  61
  62   qcom,dual-dsi-mode:
  63     type: boolean
  64     description: |
  65       Indicates if the DSI controller is driving a panel which needs
  66       2 DSI links.
  67
  68   qcom,master-dsi:
  69     type: boolean
  70     description: |
  71       Indicates if the DSI controller is the master DSI controller when
  72       qcom,dual-dsi-mode enabled.
  73
  74   qcom,sync-dual-dsi:
  75     type: boolean
  76     description: |
  77       Indicates if the DSI controller needs to sync the other DSI controller
  78       with MIPI DCS commands when qcom,dual-dsi-mode enabled.
  79
  80   assigned-clocks:
  81     maxItems: 2
  82     description: |
  83       Parents of "byte" and "pixel" for the given platform.
  84
  85   assigned-clock-parents:
  86     maxItems: 2
  87     description: |
  88       The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
  89
  90   power-domains:
  91     maxItems: 1
  92
  93   operating-points-v2: true
  94
  95   ports:
  96     $ref: "/schemas/graph.yaml#/properties/ports"
  97     description: |
  98       Contains DSI controller input and output ports as children, each
  99       containing one endpoint subnode.
 100
 101     properties:
 102       port@0:
 103         $ref: "/schemas/graph.yaml#/$defs/port-base"
 104         unevaluatedProperties: false
 105         description: |
 106           Input endpoints of the controller.
 107         properties:
 108           endpoint:
 109             $ref: /schemas/media/video-interfaces.yaml#
 110             unevaluatedProperties: false
 111             properties:
 112               data-lanes:
 113                 maxItems: 4
 114                 minItems: 4
 115                 items:
 116                   enum: [ 0, 1, 2, 3 ]
 117
 118       port@1:
 119         $ref: "/schemas/graph.yaml#/$defs/port-base"
 120         unevaluatedProperties: false
 121         description: |
 122           Output endpoints of the controller.
 123         properties:
 124           endpoint:
 125             $ref: /schemas/media/video-interfaces.yaml#
 126             unevaluatedProperties: false
 127             properties:
 128               data-lanes:
 129                 maxItems: 4
 130                 minItems: 4
 131                 items:
 132                   enum: [ 0, 1, 2, 3 ]
 133
 134     required:
 135       - port@0
 136       - port@1
 137
 138 required:
 139   - compatible
 140   - reg
 141   - reg-names
 142   - interrupts
 143   - clocks
 144   - clock-names
 145   - phys
 146   - phy-names
 147   - assigned-clocks
 148   - assigned-clock-parents
 149   - ports
 150
 151 additionalProperties: false
 152
 153 examples:
 154   - |
 155      #include <dt-bindings/interrupt-controller/arm-gic.h>
 156      #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 157      #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 158      #include <dt-bindings/power/qcom-rpmpd.h>
 159
 160      dsi@ae94000 {
 161            compatible = "qcom,mdss-dsi-ctrl";
 162            reg = <0x0ae94000 0x400>;
 163            reg-names = "dsi_ctrl";
 164
 165            #address-cells = <1>;
 166            #size-cells = <0>;
 167
 168            interrupt-parent = <&mdss>;
 169            interrupts = <4>;
 170
 171            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 172                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 173                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 174                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 175                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
 176                     <&dispcc DISP_CC_MDSS_AXI_CLK>;
 177            clock-names = "byte",
 178                          "byte_intf",
 179                          "pixel",
 180                          "core",
 181                          "iface",
 182                          "bus";
 183
 184            phys = <&dsi0_phy>;
 185            phy-names = "dsi";
 186
 187            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 188            assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
 189
 190            power-domains = <&rpmhpd SC7180_CX>;
 191            operating-points-v2 = <&dsi_opp_table>;
 192
 193            ports {
 194                   #address-cells = <1>;
 195                   #size-cells = <0>;
 196
 197                   port@0 {
 198                           reg = <0>;
 199                           dsi0_in: endpoint {
 200                                    remote-endpoint = <&dpu_intf1_out>;
 201                           };
 202                   };
 203
 204                   port@1 {
 205                           reg = <1>;
 206                           dsi0_out: endpoint {
 207                                    remote-endpoint = <&sn65dsi86_in>;
 208                                    data-lanes = <0 1 2 3>;
 209                           };
 210                   };
 211            };
 212      };
 213 ...