1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SC7280
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SC7280.
19 const: qcom,sc7280-mdss
32 - description: Display AHB clock from gcc
33 - description: Display AHB clock from dispcc
34 - description: Display core clock
45 interrupt-controller: true
47 "#address-cells": true
56 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
62 - description: Interconnect path specifying the port ids for data bus
69 - description: MDSS_CORE reset
72 "^display-controller@[0-9a-f]+$":
74 description: Node containing the properties of DPU.
78 const: qcom,sc7280-dpu
82 - description: Address offset and size for mdp register set
83 - description: Address offset and size for vbif register set
92 - description: Display hf axi clock
93 - description: Display sf axi clock
94 - description: Display ahb clock
95 - description: Display lut clock
96 - description: Display core clock
97 - description: Display vsync clock
114 operating-points-v2: true
117 $ref: /schemas/graph.yaml#/properties/ports
119 Contains the list of output ports from DPU device. These ports
120 connect to interfaces that are external to the DPU hardware,
121 such as DSI, DP etc. Each output port contains an endpoint that
122 describes how it is connected to an external interface.
126 $ref: /schemas/graph.yaml#/properties/port
127 description: DPU_INTF1 (DSI)
130 $ref: /schemas/graph.yaml#/properties/port
131 description: DPU_INTF5 (EDP)
143 - operating-points-v2
153 - interrupt-controller
157 additionalProperties: false
161 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
162 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
163 #include <dt-bindings/interrupt-controller/arm-gic.h>
164 #include <dt-bindings/interconnect/qcom,sc7280.h>
165 #include <dt-bindings/power/qcom-rpmpd.h>
167 display-subsystem@ae00000 {
168 #address-cells = <1>;
170 compatible = "qcom,sc7280-mdss";
171 reg = <0xae00000 0x1000>;
173 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
174 clocks = <&gcc GCC_DISP_AHB_CLK>,
175 <&dispcc DISP_CC_MDSS_AHB_CLK>,
176 <&dispcc DISP_CC_MDSS_MDP_CLK>;
177 clock-names = "iface",
181 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
182 interrupt-controller;
183 #interrupt-cells = <1>;
185 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
186 interconnect-names = "mdp0-mem";
188 iommus = <&apps_smmu 0x900 0x402>;
191 display-controller@ae01000 {
192 compatible = "qcom,sc7280-dpu";
193 reg = <0x0ae01000 0x8f000>,
196 reg-names = "mdp", "vbif";
198 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
199 <&gcc GCC_DISP_SF_AXI_CLK>,
200 <&dispcc DISP_CC_MDSS_AHB_CLK>,
201 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
202 <&dispcc DISP_CC_MDSS_MDP_CLK>,
203 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
211 interrupt-parent = <&mdss>;
213 power-domains = <&rpmhpd SC7280_CX>;
214 operating-points-v2 = <&mdp_opp_table>;
217 #address-cells = <1>;
222 dpu_intf1_out: endpoint {
223 remote-endpoint = <&dsi0_in>;
229 dpu_intf5_out: endpoint {
230 remote-endpoint = <&edp_in>;