1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SC7280
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SC7280.
19 const: qcom,sc7280-mdss
32 - description: Display AHB clock from gcc
33 - description: Display AHB clock from dispcc
34 - description: Display core clock
45 interrupt-controller: true
47 "#address-cells": true
56 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
62 - description: Interconnect path specifying the port ids for data bus
69 - description: MDSS_CORE reset
72 "^display-controller@[0-9a-f]+$":
74 description: Node containing the properties of DPU.
75 additionalProperties: false
79 const: qcom,sc7280-dpu
83 - description: Address offset and size for mdp register set
84 - description: Address offset and size for vbif register set
93 - description: Display hf axi clock
94 - description: Display sf axi clock
95 - description: Display ahb clock
96 - description: Display lut clock
97 - description: Display core clock
98 - description: Display vsync clock
115 operating-points-v2: true
120 $ref: /schemas/graph.yaml#/properties/ports
122 Contains the list of output ports from DPU device. These ports
123 connect to interfaces that are external to the DPU hardware,
124 such as DSI, DP etc. Each output port contains an endpoint that
125 describes how it is connected to an external interface.
129 $ref: /schemas/graph.yaml#/properties/port
130 description: DPU_INTF1 (DSI)
133 $ref: /schemas/graph.yaml#/properties/port
134 description: DPU_INTF5 (EDP)
146 - operating-points-v2
156 - interrupt-controller
160 additionalProperties: false
164 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
165 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
166 #include <dt-bindings/interrupt-controller/arm-gic.h>
167 #include <dt-bindings/interconnect/qcom,sc7280.h>
168 #include <dt-bindings/power/qcom-rpmpd.h>
170 display-subsystem@ae00000 {
171 #address-cells = <1>;
173 compatible = "qcom,sc7280-mdss";
174 reg = <0xae00000 0x1000>;
176 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
177 clocks = <&gcc GCC_DISP_AHB_CLK>,
178 <&dispcc DISP_CC_MDSS_AHB_CLK>,
179 <&dispcc DISP_CC_MDSS_MDP_CLK>;
180 clock-names = "iface",
184 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
185 interrupt-controller;
186 #interrupt-cells = <1>;
188 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
189 interconnect-names = "mdp0-mem";
191 iommus = <&apps_smmu 0x900 0x402>;
194 display-controller@ae01000 {
195 compatible = "qcom,sc7280-dpu";
196 reg = <0x0ae01000 0x8f000>,
199 reg-names = "mdp", "vbif";
201 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
202 <&gcc GCC_DISP_SF_AXI_CLK>,
203 <&dispcc DISP_CC_MDSS_AHB_CLK>,
204 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
205 <&dispcc DISP_CC_MDSS_MDP_CLK>,
206 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
214 interrupt-parent = <&mdss>;
216 power-domains = <&rpmhpd SC7280_CX>;
217 operating-points-v2 = <&mdp_opp_table>;
220 #address-cells = <1>;
225 dpu_intf1_out: endpoint {
226 remote-endpoint = <&dsi0_in>;
232 dpu_intf5_out: endpoint {
233 remote-endpoint = <&edp_in>;