1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SC7180 target
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SC7180 target.
20 - const: qcom,sc7180-mdss
33 - description: Display AHB clock from gcc
34 - description: Display AHB clock from dispcc
35 - description: Display core clock
46 interrupt-controller: true
48 "#address-cells": true
57 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
63 - description: Interconnect path specifying the port ids for data bus
70 - description: MDSS_CORE reset
73 "^display-controller@[0-9a-f]+$":
75 description: Node containing the properties of DPU.
80 - const: qcom,sc7180-dpu
84 - description: Address offset and size for mdp register set
85 - description: Address offset and size for vbif register set
94 - description: Display hf axi clock
95 - description: Display ahb clock
96 - description: Display rotator clock
97 - description: Display lut clock
98 - description: Display core clock
99 - description: Display vsync clock
116 operating-points-v2: true
119 $ref: /schemas/graph.yaml#/properties/ports
121 Contains the list of output ports from DPU device. These ports
122 connect to interfaces that are external to the DPU hardware,
123 such as DSI, DP etc. Each output port contains an endpoint that
124 describes how it is connected to an external interface.
128 $ref: /schemas/graph.yaml#/properties/port
129 description: DPU_INTF1 (DSI1)
132 $ref: /schemas/graph.yaml#/properties/port
133 description: DPU_INTF0 (DP)
145 - operating-points-v2
155 - interrupt-controller
159 additionalProperties: false
163 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
164 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
165 #include <dt-bindings/interrupt-controller/arm-gic.h>
166 #include <dt-bindings/interconnect/qcom,sdm845.h>
167 #include <dt-bindings/power/qcom-rpmpd.h>
169 display-subsystem@ae00000 {
170 #address-cells = <1>;
172 compatible = "qcom,sc7180-mdss";
173 reg = <0xae00000 0x1000>;
175 power-domains = <&dispcc MDSS_GDSC>;
176 clocks = <&gcc GCC_DISP_AHB_CLK>,
177 <&dispcc DISP_CC_MDSS_AHB_CLK>,
178 <&dispcc DISP_CC_MDSS_MDP_CLK>;
179 clock-names = "iface", "ahb", "core";
181 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
182 interrupt-controller;
183 #interrupt-cells = <1>;
185 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
186 interconnect-names = "mdp0-mem";
188 iommus = <&apps_smmu 0x800 0x2>;
191 display-controller@ae01000 {
192 compatible = "qcom,sc7180-dpu";
193 reg = <0x0ae01000 0x8f000>,
196 reg-names = "mdp", "vbif";
198 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
199 <&dispcc DISP_CC_MDSS_AHB_CLK>,
200 <&dispcc DISP_CC_MDSS_ROT_CLK>,
201 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
202 <&dispcc DISP_CC_MDSS_MDP_CLK>,
203 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
204 clock-names = "bus", "iface", "rot", "lut", "core",
207 interrupt-parent = <&mdss>;
209 power-domains = <&rpmhpd SC7180_CX>;
210 operating-points-v2 = <&mdp_opp_table>;
213 #address-cells = <1>;
218 dpu_intf1_out: endpoint {
219 remote-endpoint = <&dsi0_in>;
225 dpu_intf0_out: endpoint {
226 remote-endpoint = <&dp_in>;