Documentation/devicetree/bindings/display/msm/dpu-qcm2290.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display DPU dt properties for QCM2290 target
   8
   9 maintainers:
  10   - Loic Poulain <loic.poulain@linaro.org>
  11
  12 description: |
  13   Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  14   sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
  15   and DPU are mentioned for QCM2290 target.
  16
  17 properties:
  18   compatible:
  19     items:
  20       - const: qcom,qcm2290-mdss
  21
  22   reg:
  23     maxItems: 1
  24
  25   reg-names:
  26     const: mdss
  27
  28   power-domains:
  29     maxItems: 1
  30
  31   clocks:
  32     items:
  33       - description: Display AHB clock from gcc
  34       - description: Display AXI clock
  35       - description: Display core clock
  36
  37   clock-names:
  38     items:
  39       - const: iface
  40       - const: bus
  41       - const: core
  42
  43   interrupts:
  44     maxItems: 1
  45
  46   interrupt-controller: true
  47
  48   "#address-cells": true
  49
  50   "#size-cells": true
  51
  52   "#interrupt-cells":
  53     const: 1
  54
  55   iommus:
  56     items:
  57       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
  58       - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
  59
  60   ranges: true
  61
  62   interconnects:
  63     items:
  64       - description: Interconnect path specifying the port ids for data bus
  65
  66   interconnect-names:
  67     const: mdp0-mem
  68
  69   resets:
  70     items:
  71       - description: MDSS_CORE reset
  72
  73 patternProperties:
  74   "^display-controller@[0-9a-f]+$":
  75     type: object
  76     description: Node containing the properties of DPU.
  77     additionalProperties: false
  78
  79     properties:
  80       compatible:
  81         items:
  82           - const: qcom,qcm2290-dpu
  83
  84       reg:
  85         items:
  86           - description: Address offset and size for mdp register set
  87           - description: Address offset and size for vbif register set
  88
  89       reg-names:
  90         items:
  91           - const: mdp
  92           - const: vbif
  93
  94       clocks:
  95         items:
  96           - description: Display AXI clock from gcc
  97           - description: Display AHB clock from dispcc
  98           - description: Display core clock from dispcc
  99           - description: Display lut clock from dispcc
 100           - description: Display vsync clock from dispcc
 101
 102       clock-names:
 103         items:
 104           - const: bus
 105           - const: iface
 106           - const: core
 107           - const: lut
 108           - const: vsync
 109
 110       interrupts:
 111         maxItems: 1
 112
 113       power-domains:
 114         maxItems: 1
 115
 116       operating-points-v2: true
 117       opp-table:
 118         type: object
 119
 120       ports:
 121         $ref: /schemas/graph.yaml#/properties/ports
 122         description: |
 123           Contains the list of output ports from DPU device. These ports
 124           connect to interfaces that are external to the DPU hardware,
 125           such as DSI. Each output port contains an endpoint that
 126           describes how it is connected to an external interface.
 127
 128         properties:
 129           port@0:
 130             $ref: /schemas/graph.yaml#/properties/port
 131             description: DPU_INTF1 (DSI1)
 132
 133         required:
 134           - port@0
 135
 136     required:
 137       - compatible
 138       - reg
 139       - reg-names
 140       - clocks
 141       - interrupts
 142       - power-domains
 143       - operating-points-v2
 144       - ports
 145
 146 required:
 147   - compatible
 148   - reg
 149   - reg-names
 150   - power-domains
 151   - clocks
 152   - interrupts
 153   - interrupt-controller
 154   - iommus
 155   - ranges
 156
 157 additionalProperties: false
 158
 159 examples:
 160   - |
 161     #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
 162     #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
 163     #include <dt-bindings/interrupt-controller/arm-gic.h>
 164     #include <dt-bindings/interconnect/qcom,qcm2290.h>
 165     #include <dt-bindings/power/qcom-rpmpd.h>
 166
 167     mdss: mdss@5e00000 {
 168         #address-cells = <1>;
 169         #size-cells = <1>;
 170         compatible = "qcom,qcm2290-mdss";
 171         reg = <0x05e00000 0x1000>;
 172         reg-names = "mdss";
 173         power-domains = <&dispcc MDSS_GDSC>;
 174         clocks = <&gcc GCC_DISP_AHB_CLK>,
 175                  <&gcc GCC_DISP_HF_AXI_CLK>,
 176                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
 177         clock-names = "iface", "bus", "core";
 178
 179         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 180         interrupt-controller;
 181         #interrupt-cells = <1>;
 182
 183         interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
 184         interconnect-names = "mdp0-mem";
 185
 186         iommus = <&apps_smmu 0x420 0x2>,
 187                  <&apps_smmu 0x421 0x0>;
 188         ranges;
 189
 190         mdss_mdp: display-controller@5e01000 {
 191                 compatible = "qcom,qcm2290-dpu";
 192                 reg = <0x05e01000 0x8f000>,
 193                       <0x05eb0000 0x2008>;
 194                 reg-names = "mdp", "vbif";
 195
 196                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
 197                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
 198                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
 199                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 200                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 201                 clock-names = "bus", "iface", "core", "lut", "vsync";
 202
 203                 operating-points-v2 = <&mdp_opp_table>;
 204                 power-domains = <&rpmpd QCM2290_VDDCX>;
 205
 206                 interrupt-parent = <&mdss>;
 207                 interrupts = <0>;
 208
 209                 ports {
 210                         #address-cells = <1>;
 211                         #size-cells = <0>;
 212
 213                         port@0 {
 214                                 reg = <0>;
 215                                 dpu_intf1_out: endpoint {
 216                                         remote-endpoint = <&dsi0_in>;
 217                                 };
 218                         };
 219                 };
 220          };
 221     };
 222 ...