1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dpu-qcm2290.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for QCM2290 target
10 - Loic Poulain <loic.poulain@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15 and DPU are mentioned for QCM2290 target.
20 - const: qcom,qcm2290-mdss
33 - description: Display AHB clock from gcc
34 - description: Display AXI clock
35 - description: Display core clock
46 interrupt-controller: true
48 "#address-cells": true
57 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
58 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
64 - description: Interconnect path specifying the port ids for data bus
71 - description: MDSS_CORE reset
74 "^display-controller@[0-9a-f]+$":
76 description: Node containing the properties of DPU.
81 - const: qcom,qcm2290-dpu
85 - description: Address offset and size for mdp register set
86 - description: Address offset and size for vbif register set
95 - description: Display AXI clock from gcc
96 - description: Display AHB clock from dispcc
97 - description: Display core clock from dispcc
98 - description: Display lut clock from dispcc
99 - description: Display vsync clock from dispcc
115 operating-points-v2: true
118 $ref: /schemas/graph.yaml#/properties/ports
120 Contains the list of output ports from DPU device. These ports
121 connect to interfaces that are external to the DPU hardware,
122 such as DSI. Each output port contains an endpoint that
123 describes how it is connected to an external interface.
127 $ref: /schemas/graph.yaml#/properties/port
128 description: DPU_INTF1 (DSI1)
140 - operating-points-v2
150 - interrupt-controller
154 additionalProperties: false
158 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
159 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
160 #include <dt-bindings/interrupt-controller/arm-gic.h>
161 #include <dt-bindings/interconnect/qcom,qcm2290.h>
162 #include <dt-bindings/power/qcom-rpmpd.h>
165 #address-cells = <1>;
167 compatible = "qcom,qcm2290-mdss";
168 reg = <0x05e00000 0x1000>;
170 power-domains = <&dispcc MDSS_GDSC>;
171 clocks = <&gcc GCC_DISP_AHB_CLK>,
172 <&gcc GCC_DISP_HF_AXI_CLK>,
173 <&dispcc DISP_CC_MDSS_MDP_CLK>;
174 clock-names = "iface", "bus", "core";
176 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-controller;
178 #interrupt-cells = <1>;
180 interconnects = <&mmrt_virt MASTER_MDP0 &bimc SLAVE_EBI1>;
181 interconnect-names = "mdp0-mem";
183 iommus = <&apps_smmu 0x420 0x2>,
184 <&apps_smmu 0x421 0x0>;
187 mdss_mdp: display-controller@5e01000 {
188 compatible = "qcom,qcm2290-dpu";
189 reg = <0x05e01000 0x8f000>,
191 reg-names = "mdp", "vbif";
193 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
194 <&dispcc DISP_CC_MDSS_AHB_CLK>,
195 <&dispcc DISP_CC_MDSS_MDP_CLK>,
196 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
197 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
198 clock-names = "bus", "iface", "core", "lut", "vsync";
200 operating-points-v2 = <&mdp_opp_table>;
201 power-domains = <&rpmpd QCM2290_VDDCX>;
203 interrupt-parent = <&mdss>;
207 #address-cells = <1>;
212 dpu_intf1_out: endpoint {
213 remote-endpoint = <&dsi0_in>;