Documentation/devicetree/bindings/display/msm/dp-controller.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: MSM Display Port Controller
   8
   9 maintainers:
  10   - Kuogee Hsieh <quic_khsieh@quicinc.com>
  11
  12 description: |
  13   Device tree bindings for DisplayPort host controller for MSM targets
  14   that are compatible with VESA DisplayPort interface specification.
  15
  16 properties:
  17   compatible:
  18     enum:
  19       - qcom,sc7180-dp
  20       - qcom,sc7280-dp
  21       - qcom,sc7280-edp
  22       - qcom,sc8180x-dp
  23       - qcom,sc8180x-edp
  24       - qcom,sm8350-dp
  25
  26   reg:
  27     minItems: 4
  28     items:
  29       - description: ahb register block
  30       - description: aux register block
  31       - description: link register block
  32       - description: p0 register block
  33       - description: p1 register block
  34
  35   interrupts:
  36     maxItems: 1
  37
  38   clocks:
  39     items:
  40       - description: AHB clock to enable register access
  41       - description: Display Port AUX clock
  42       - description: Display Port Link clock
  43       - description: Link interface clock between DP and PHY
  44       - description: Display Port Pixel clock
  45
  46   clock-names:
  47     items:
  48       - const: core_iface
  49       - const: core_aux
  50       - const: ctrl_link
  51       - const: ctrl_link_iface
  52       - const: stream_pixel
  53
  54   assigned-clocks:
  55     items:
  56       - description: link clock source
  57       - description: pixel clock source
  58
  59   assigned-clock-parents:
  60     items:
  61       - description: phy 0 parent
  62       - description: phy 1 parent
  63
  64   phys:
  65     maxItems: 1
  66
  67   phy-names:
  68     items:
  69       - const: dp
  70
  71   operating-points-v2:
  72     maxItems: 1
  73
  74   opp-table: true
  75
  76   power-domains:
  77     maxItems: 1
  78
  79   aux-bus:
  80     $ref: /schemas/display/dp-aux-bus.yaml#
  81
  82   data-lanes:
  83     $ref: /schemas/types.yaml#/definitions/uint32-array
  84     minItems: 1
  85     maxItems: 4
  86     items:
  87       maximum: 3
  88
  89   "#sound-dai-cells":
  90     const: 0
  91
  92   vdda-0p9-supply:
  93     deprecated: true
  94   vdda-1p2-supply:
  95     deprecated: true
  96
  97   ports:
  98     $ref: /schemas/graph.yaml#/properties/ports
  99     properties:
 100       port@0:
 101         $ref: /schemas/graph.yaml#/properties/port
 102         description: Input endpoint of the controller
 103
 104       port@1:
 105         $ref: /schemas/graph.yaml#/properties/port
 106         description: Output endpoint of the controller
 107
 108 required:
 109   - compatible
 110   - reg
 111   - interrupts
 112   - clocks
 113   - clock-names
 114   - phys
 115   - phy-names
 116   - power-domains
 117   - ports
 118
 119 allOf:
 120   # AUX BUS does not exist on DP controllers
 121   # Audio output also is present only on DP output
 122   # p1 regions is present on DP, but not on eDP
 123   - if:
 124       properties:
 125         compatible:
 126           contains:
 127             enum:
 128               - qcom,sc7280-edp
 129               - qcom,sc8180x-edp
 130     then:
 131       properties:
 132         "#sound-dai-cells": false
 133         reg:
 134           maxItems: 4
 135     else:
 136       properties:
 137         aux-bus: false
 138         reg:
 139           minItems: 5
 140       required:
 141         - "#sound-dai-cells"
 142
 143 additionalProperties: false
 144
 145 examples:
 146   - |
 147     #include <dt-bindings/interrupt-controller/arm-gic.h>
 148     #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
 149     #include <dt-bindings/power/qcom-rpmpd.h>
 150
 151     displayport-controller@ae90000 {
 152         compatible = "qcom,sc7180-dp";
 153         reg = <0xae90000 0x200>,
 154               <0xae90200 0x200>,
 155               <0xae90400 0xc00>,
 156               <0xae91000 0x400>,
 157               <0xae91400 0x400>;
 158         interrupt-parent = <&mdss>;
 159         interrupts = <12>;
 160         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 161                  <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
 162                  <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
 163                  <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
 164                  <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
 165         clock-names = "core_iface", "core_aux",
 166                       "ctrl_link",
 167                       "ctrl_link_iface", "stream_pixel";
 168
 169         assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
 170                           <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
 171
 172         assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
 173
 174         phys = <&dp_phy>;
 175         phy-names = "dp";
 176
 177         #sound-dai-cells = <0>;
 178
 179         power-domains = <&rpmhpd SC7180_CX>;
 180
 181         ports {
 182             #address-cells = <1>;
 183             #size-cells = <0>;
 184
 185             port@0 {
 186                 reg = <0>;
 187                 endpoint {
 188                     remote-endpoint = <&dpu_intf0_out>;
 189                 };
 190             };
 191
 192             port@1 {
 193                 reg = <1>;
 194                 endpoint {
 195                     remote-endpoint = <&typec>;
 196                 };
 197             };
 198         };
 199     };
 200 ...