1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek display merge
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek display merge, namely MERGE, is used to merge two slice-per-line
15 inputs into one side-by-side output.
16 MERGE device node must be siblings to the central MMSYS_CONFIG node.
17 For a description of the MMSYS_CONFIG binding, see
18 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
25 - const: mediatek,mt8173-disp-merge
27 - const: mediatek,mt8195-disp-merge
36 description: A phandle and PM domain specifier as defined by bindings of
37 the power controller specified by phandle. See
38 Documentation/devicetree/bindings/power/power-domain.yaml for details.
52 mediatek,merge-fifo-en:
54 The setting of merge fifo is mainly provided for the display latency
55 buffer to ensure that the back-end panel display data will not be
56 underrun, a little more data is needed in the fifo.
57 According to the merge fifo settings, when the water level is detected
58 to be insufficient, it will trigger RDMA sending ultra and preulra
59 command to SMI to speed up the data rate.
63 description: Support mute function. Mute the content of merge output.
66 mediatek,gce-client-reg:
67 description: The register of client driver can be configured by gce with
68 4 arguments defined in this property, such as phandle of gce, subsys id,
69 register offset and size. Each GCE subsys id is mapping to a client
70 defined in the header include/dt-bindings/gce/<chip>-gce.h.
71 $ref: /schemas/types.yaml#/definitions/phandle-array
75 description: reset controller
76 See Documentation/devicetree/bindings/reset/reset.txt for details.
85 additionalProperties: false
89 #include <dt-bindings/interrupt-controller/arm-gic.h>
90 #include <dt-bindings/clock/mt8173-clk.h>
91 #include <dt-bindings/power/mt8173-power.h>
98 compatible = "mediatek,mt8173-disp-merge";
99 reg = <0 0x14017000 0 0x1000>;
100 power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
101 clocks = <&mmsys CLK_MM_DISP_MERGE>;
102 clock-names = "merge";