Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt

   1 Mediatek DSI Device
   2 ===================
   3
   4 The Mediatek DSI function block is a sink of the display subsystem and can
   5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
   6 channel output.
   7
   8 Required properties:
   9 - compatible: "mediatek,<chip>-dsi"
  10 - the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
  11 - reg: Physical base address and length of the controller's registers
  12 - interrupts: The interrupt signal from the function block.
  13 - clocks: device clocks
  14   See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
  15 - clock-names: must contain "engine", "digital", and "hs"
  16 - phys: phandle link to the MIPI D-PHY controller.
  17 - phy-names: must contain "dphy"
  18 - port: Output port node with endpoint definitions as described in
  19   Documentation/devicetree/bindings/graph.txt. This port should be connected
  20   to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
  21
  22 Optional properties:
  23 - resets: list of phandle + reset specifier pair, as described in [1].
  24
  25 [1] Documentation/devicetree/bindings/reset/reset.txt
  26
  27 MIPI TX Configuration Module
  28 ============================
  29
  30 See phy/mediatek,dsi-phy.yaml
  31
  32 Example:
  33
  34 mipi_tx0: mipi-dphy@10215000 {
  35         compatible = "mediatek,mt8173-mipi-tx";
  36         reg = <0 0x10215000 0 0x1000>;
  37         clocks = <&clk26m>;
  38         clock-output-names = "mipi_tx0_pll";
  39         #clock-cells = <0>;
  40         #phy-cells = <0>;
  41         drive-strength-microamp = <4600>;
  42         nvmem-cells= <&mipi_tx_calibration>;
  43         nvmem-cell-names = "calibration-data";
  44 };
  45
  46 dsi0: dsi@1401b000 {
  47         compatible = "mediatek,mt8173-dsi";
  48         reg = <0 0x1401b000 0 0x1000>;
  49         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
  50         clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
  51                  <&mipi_tx0>;
  52         clock-names = "engine", "digital", "hs";
  53         resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>;
  54         phys = <&mipi_tx0>;
  55         phy-names = "dphy";
  56
  57         port {
  58                 dsi0_out: endpoint {
  59                         remote-endpoint = <&panel_in>;
  60                 };
  61         };
  62 };