1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DPI and DP_INTF Controller
10 - CK Hu <ck.hu@mediatek.com>
11 - Jitao shi <jitao.shi@mediatek.com>
14 The MediaTek DPI and DP_INTF function blocks are a sink of the display
15 subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
27 - mediatek,mt8195-dp-intf
37 - description: Pixel Clock
38 - description: Engine Clock
39 - description: DPI PLL
56 $ref: /schemas/graph.yaml#/properties/port
58 Output port node. This port should be connected to the input port of an
59 attached HDMI, LVDS or DisplayPort encoder chip.
69 additionalProperties: false
73 #include <dt-bindings/interrupt-controller/arm-gic.h>
74 #include <dt-bindings/clock/mt8173-clk.h>
77 compatible = "mediatek,mt8173-dpi";
78 reg = <0x1401d000 0x1000>;
79 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
80 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
81 <&mmsys CLK_MM_DPI_ENGINE>,
82 <&apmixedsys CLK_APMIXED_TVDPLL>;
83 clock-names = "pixel", "engine", "pll";
84 pinctrl-names = "default", "sleep";
85 pinctrl-0 = <&dpi_pin_func>;
86 pinctrl-1 = <&dpi_pin_idle>;
90 remote-endpoint = <&hdmi0_in>;