Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: MediaTek Display Port Controller
   8
   9 maintainers:
  10   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
  11   - Jitao shi <jitao.shi@mediatek.com>
  12
  13 description: |
  14   MediaTek DP and eDP are different hardwares and there are some features
  15   which are not supported for eDP. For example, audio is not supported for
  16   eDP. Therefore, we need to use two different compatibles to describe them.
  17   In addition, We just need to enable the power domain of DP, so the clock
  18   of DP is generated by itself and we are not using other PLL to generate
  19   clocks.
  20
  21 properties:
  22   compatible:
  23     enum:
  24       - mediatek,mt8195-dp-tx
  25       - mediatek,mt8195-edp-tx
  26
  27   reg:
  28     maxItems: 1
  29
  30   nvmem-cells:
  31     maxItems: 1
  32     description: efuse data for display port calibration
  33
  34   nvmem-cell-names:
  35     const: dp_calibration_data
  36
  37   power-domains:
  38     maxItems: 1
  39
  40   interrupts:
  41     maxItems: 1
  42
  43   ports:
  44     $ref: /schemas/graph.yaml#/properties/ports
  45     properties:
  46       port@0:
  47         $ref: /schemas/graph.yaml#/properties/port
  48         description: Input endpoint of the controller, usually dp_intf
  49
  50       port@1:
  51         $ref: /schemas/graph.yaml#/$defs/port-base
  52         unevaluatedProperties: false
  53         description: Output endpoint of the controller
  54         properties:
  55           endpoint:
  56             $ref: /schemas/media/video-interfaces.yaml#
  57             unevaluatedProperties: false
  58             properties:
  59               data-lanes:
  60                 description: |
  61                   number of lanes supported by the hardware.
  62                   The possible values:
  63                   0       - For 1 lane enabled in IP.
  64                   0 1     - For 2 lanes enabled in IP.
  65                   0 1 2 3 - For 4 lanes enabled in IP.
  66                 minItems: 1
  67                 maxItems: 4
  68             required:
  69               - data-lanes
  70
  71     required:
  72       - port@0
  73       - port@1
  74
  75   max-linkrate-mhz:
  76     enum: [ 1620, 2700, 5400, 8100 ]
  77     description: maximum link rate supported by the hardware.
  78
  79 required:
  80   - compatible
  81   - reg
  82   - interrupts
  83   - ports
  84   - max-linkrate-mhz
  85
  86 additionalProperties: false
  87
  88 examples:
  89   - |
  90     #include <dt-bindings/interrupt-controller/arm-gic.h>
  91     #include <dt-bindings/power/mt8195-power.h>
  92     dptx@1c600000 {
  93         compatible = "mediatek,mt8195-dp-tx";
  94         reg = <0x1c600000 0x8000>;
  95         power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
  96         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
  97         max-linkrate-mhz = <8100>;
  98
  99         ports {
 100             #address-cells = <1>;
 101             #size-cells = <0>;
 102
 103             port@0 {
 104                 reg = <0>;
 105                 dptx_in: endpoint {
 106                     remote-endpoint = <&dp_intf0_out>;
 107                 };
 108             };
 109             port@1 {
 110                 reg = <1>;
 111                 dptx_out: endpoint {
 112                     data-lanes = <0 1 2 3>;
 113                 };
 114             };
 115         };
 116     };