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[releases.git] / Documentation / devicetree / bindings / display / brcm,bcm2835-dsi0.yaml
1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/display/brcm,bcm2835-dsi0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Broadcom VC4 (VideoCore4) DSI Controller
8
9 maintainers:
10   - Eric Anholt <eric@anholt.net>
11
12 allOf:
13   - $ref: dsi-controller.yaml#
14
15 properties:
16   "#clock-cells":
17     const: 1
18
19   compatible:
20     enum:
21       - brcm,bcm2835-dsi0
22       - brcm,bcm2835-dsi1
23
24   reg:
25     maxItems: 1
26
27   clocks:
28     items:
29       - description: The DSI PLL clock feeding the DSI analog PHY
30       - description: The DSI ESC clock
31       - description: The DSI pixel clock
32
33   clock-names:
34     items:
35       - const: phy
36       - const: escape
37       - const: pixel
38
39   clock-output-names: true
40     # FIXME: The meta-schemas don't seem to allow it for now
41     # items:
42     #   - description: The DSI byte clock for the PHY
43     #   - description: The DSI DDR2 clock
44     #   - description: The DSI DDR clock
45
46   interrupts:
47     maxItems: 1
48
49 required:
50   - "#clock-cells"
51   - compatible
52   - reg
53   - clocks
54   - clock-names
55   - clock-output-names
56   - interrupts
57
58 unevaluatedProperties: false
59
60 examples:
61   - |
62     #include <dt-bindings/clock/bcm2835.h>
63
64     dsi1: dsi@7e700000 {
65         compatible = "brcm,bcm2835-dsi1";
66         reg = <0x7e700000 0x8c>;
67         interrupts = <2 12>;
68         #address-cells = <1>;
69         #size-cells = <0>;
70         #clock-cells = <1>;
71
72         clocks = <&clocks BCM2835_PLLD_DSI1>,
73                  <&clocks BCM2835_CLOCK_DSI1E>,
74                  <&clocks BCM2835_CLOCK_DSI1P>;
75         clock-names = "phy", "escape", "pixel";
76
77         clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";
78
79         pitouchscreen: panel@0 {
80             compatible = "raspberrypi,touchscreen";
81             reg = <0>;
82
83             /* ... */
84         };
85     };
86
87 ...