1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra30 Activity Monitor
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The activity monitor block collects statistics about the behaviour of other
16 components in the system. This information can be used to derive the rate at
17 which the external memory needs to be clocked in order to serve all requests
18 from the monitored clients.
23 - nvidia,tegra30-actmon
24 - nvidia,tegra114-actmon
25 - nvidia,tegra124-actmon
26 - nvidia,tegra210-actmon
57 Should include name of the interconnect path for each interconnect
58 entry. Consult TRM documentation for information about available
59 memory clients, see MEMORY CONTROLLER and ACTIVITY MONITOR sections.
63 Should contain freqs and voltages and opp-supported-hw property, which
64 is a bitfield indicating SoC speedo ID mask.
82 additionalProperties: false
86 #include <dt-bindings/memory/tegra30-mc.h>
88 mc: memory-controller@7000f000 {
89 compatible = "nvidia,tegra30-mc";
90 reg = <0x7000f000 0x400>;
94 interrupts = <0 77 4>;
98 #interconnect-cells = <1>;
101 emc: external-memory-controller@7000f400 {
102 compatible = "nvidia,tegra30-emc";
103 reg = <0x7000f400 0x400>;
104 interrupts = <0 78 4>;
107 nvidia,memory-controller = <&mc>;
108 operating-points-v2 = <&dvfs_opp_table>;
109 power-domains = <&domain>;
111 #interconnect-cells = <0>;
115 compatible = "nvidia,tegra30-actmon";
116 reg = <0x6000c800 0x400>;
117 interrupts = <0 45 4>;
118 clocks = <&clk 119>, <&clk 57>;
119 clock-names = "actmon", "emc";
121 reset-names = "actmon";
122 operating-points-v2 = <&dvfs_opp_table>;
123 interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
124 interconnect-names = "cpu-read";
125 #cooling-cells = <2>;