1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. CPUFREQ
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
15 SoCs to manage frequency in hardware. It is capable of controlling frequency
16 for multiple clusters.
21 - description: v1 of CPUFREQ HW
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
27 - qcom,sdm845-cpufreq-hw
28 - qcom,sm6115-cpufreq-hw
29 - qcom,sm6350-cpufreq-hw
30 - qcom,sm8150-cpufreq-hw
31 - const: qcom,cpufreq-hw
33 - description: v2 of CPUFREQ HW (EPSS)
36 - qcom,qdu1000-cpufreq-epss
37 - qcom,sa8775p-cpufreq-epss
38 - qcom,sc7280-cpufreq-epss
39 - qcom,sc8280xp-cpufreq-epss
40 - qcom,sdx75-cpufreq-epss
41 - qcom,sm6375-cpufreq-epss
42 - qcom,sm8250-cpufreq-epss
43 - qcom,sm8350-cpufreq-epss
44 - qcom,sm8450-cpufreq-epss
45 - qcom,sm8550-cpufreq-epss
46 - qcom,sm8650-cpufreq-epss
47 - const: qcom,cpufreq-epss
52 - description: Frequency domain 0 register region
53 - description: Frequency domain 1 register region
54 - description: Frequency domain 2 register region
55 - description: Frequency domain 3 register region
67 - description: XO Clock
68 - description: GPLL0 Clock
98 - '#freq-domain-cells'
100 additionalProperties: false
108 - qcom,qcm2290-cpufreq-hw
131 - qcom,qdu1000-cpufreq-epss
132 - qcom,sc7180-cpufreq-hw
133 - qcom,sc8280xp-cpufreq-epss
134 - qcom,sdm670-cpufreq-hw
135 - qcom,sdm845-cpufreq-hw
136 - qcom,sm6115-cpufreq-hw
137 - qcom,sm6350-cpufreq-hw
138 - qcom,sm6375-cpufreq-epss
161 - qcom,sc7280-cpufreq-epss
162 - qcom,sm8250-cpufreq-epss
163 - qcom,sm8350-cpufreq-epss
164 - qcom,sm8450-cpufreq-epss
165 - qcom,sm8550-cpufreq-epss
188 - qcom,sm8150-cpufreq-hw
199 # On some SoCs the Prime core shares the LMH irq with Big cores
210 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
211 #include <dt-bindings/clock/qcom,rpmh.h>
213 // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
214 // switch DCVS state together.
216 #address-cells = <2>;
221 compatible = "qcom,kryo385";
223 enable-method = "psci";
224 next-level-cache = <&L2_0>;
225 qcom,freq-domain = <&cpufreq_hw 0>;
226 clocks = <&cpufreq_hw 0>;
228 compatible = "cache";
231 next-level-cache = <&L3_0>;
233 compatible = "cache";
242 compatible = "qcom,kryo385";
244 enable-method = "psci";
245 next-level-cache = <&L2_100>;
246 qcom,freq-domain = <&cpufreq_hw 0>;
247 clocks = <&cpufreq_hw 0>;
249 compatible = "cache";
252 next-level-cache = <&L3_0>;
258 compatible = "qcom,kryo385";
260 enable-method = "psci";
261 next-level-cache = <&L2_200>;
262 qcom,freq-domain = <&cpufreq_hw 0>;
263 clocks = <&cpufreq_hw 0>;
265 compatible = "cache";
268 next-level-cache = <&L3_0>;
274 compatible = "qcom,kryo385";
276 enable-method = "psci";
277 next-level-cache = <&L2_300>;
278 qcom,freq-domain = <&cpufreq_hw 0>;
279 clocks = <&cpufreq_hw 0>;
281 compatible = "cache";
284 next-level-cache = <&L3_0>;
290 compatible = "qcom,kryo385";
292 enable-method = "psci";
293 next-level-cache = <&L2_400>;
294 qcom,freq-domain = <&cpufreq_hw 1>;
295 clocks = <&cpufreq_hw 1>;
297 compatible = "cache";
300 next-level-cache = <&L3_0>;
306 compatible = "qcom,kryo385";
308 enable-method = "psci";
309 next-level-cache = <&L2_500>;
310 qcom,freq-domain = <&cpufreq_hw 1>;
311 clocks = <&cpufreq_hw 1>;
313 compatible = "cache";
316 next-level-cache = <&L3_0>;
322 compatible = "qcom,kryo385";
324 enable-method = "psci";
325 next-level-cache = <&L2_600>;
326 qcom,freq-domain = <&cpufreq_hw 1>;
327 clocks = <&cpufreq_hw 1>;
329 compatible = "cache";
332 next-level-cache = <&L3_0>;
338 compatible = "qcom,kryo385";
340 enable-method = "psci";
341 next-level-cache = <&L2_700>;
342 qcom,freq-domain = <&cpufreq_hw 1>;
343 clocks = <&cpufreq_hw 1>;
345 compatible = "cache";
348 next-level-cache = <&L3_0>;
354 #address-cells = <1>;
358 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
359 reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
360 reg-names = "freq-domain0", "freq-domain1";
362 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
363 clock-names = "xo", "alternate";
365 #freq-domain-cells = <1>;