Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. CPUFREQ
   8
   9 maintainers:
  10   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  11
  12 description: |
  13
  14   CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
  15   SoCs to manage frequency in hardware. It is capable of controlling frequency
  16   for multiple clusters.
  17
  18 properties:
  19   compatible:
  20     oneOf:
  21       - description: v1 of CPUFREQ HW
  22         items:
  23           - enum:
  24               - qcom,qcm2290-cpufreq-hw
  25               - qcom,sc7180-cpufreq-hw
  26               - qcom,sdm670-cpufreq-hw
  27               - qcom,sdm845-cpufreq-hw
  28               - qcom,sm6115-cpufreq-hw
  29               - qcom,sm6350-cpufreq-hw
  30               - qcom,sm8150-cpufreq-hw
  31           - const: qcom,cpufreq-hw
  32
  33       - description: v2 of CPUFREQ HW (EPSS)
  34         items:
  35           - enum:
  36               - qcom,qdu1000-cpufreq-epss
  37               - qcom,sa8775p-cpufreq-epss
  38               - qcom,sc7280-cpufreq-epss
  39               - qcom,sc8280xp-cpufreq-epss
  40               - qcom,sdx75-cpufreq-epss
  41               - qcom,sm6375-cpufreq-epss
  42               - qcom,sm8250-cpufreq-epss
  43               - qcom,sm8350-cpufreq-epss
  44               - qcom,sm8450-cpufreq-epss
  45               - qcom,sm8550-cpufreq-epss
  46               - qcom,sm8650-cpufreq-epss
  47           - const: qcom,cpufreq-epss
  48
  49   reg:
  50     minItems: 1
  51     items:
  52       - description: Frequency domain 0 register region
  53       - description: Frequency domain 1 register region
  54       - description: Frequency domain 2 register region
  55       - description: Frequency domain 3 register region
  56
  57   reg-names:
  58     minItems: 1
  59     items:
  60       - const: freq-domain0
  61       - const: freq-domain1
  62       - const: freq-domain2
  63       - const: freq-domain3
  64
  65   clocks:
  66     items:
  67       - description: XO Clock
  68       - description: GPLL0 Clock
  69
  70   clock-names:
  71     items:
  72       - const: xo
  73       - const: alternate
  74
  75   interrupts:
  76     minItems: 1
  77     maxItems: 4
  78
  79   interrupt-names:
  80     minItems: 1
  81     items:
  82       - const: dcvsh-irq-0
  83       - const: dcvsh-irq-1
  84       - const: dcvsh-irq-2
  85       - const: dcvsh-irq-3
  86
  87   '#freq-domain-cells':
  88     const: 1
  89
  90   '#clock-cells':
  91     const: 1
  92
  93 required:
  94   - compatible
  95   - reg
  96   - clocks
  97   - clock-names
  98   - '#freq-domain-cells'
  99
 100 additionalProperties: false
 101
 102 allOf:
 103   - if:
 104       properties:
 105         compatible:
 106           contains:
 107             enum:
 108               - qcom,qcm2290-cpufreq-hw
 109     then:
 110       properties:
 111         reg:
 112           minItems: 1
 113           maxItems: 1
 114
 115         reg-names:
 116           minItems: 1
 117           maxItems: 1
 118
 119         interrupts:
 120           minItems: 1
 121           maxItems: 1
 122
 123         interrupt-names:
 124           minItems: 1
 125
 126   - if:
 127       properties:
 128         compatible:
 129           contains:
 130             enum:
 131               - qcom,qdu1000-cpufreq-epss
 132               - qcom,sc7180-cpufreq-hw
 133               - qcom,sc8280xp-cpufreq-epss
 134               - qcom,sdm670-cpufreq-hw
 135               - qcom,sdm845-cpufreq-hw
 136               - qcom,sm6115-cpufreq-hw
 137               - qcom,sm6350-cpufreq-hw
 138               - qcom,sm6375-cpufreq-epss
 139     then:
 140       properties:
 141         reg:
 142           minItems: 2
 143           maxItems: 2
 144
 145         reg-names:
 146           minItems: 2
 147           maxItems: 2
 148
 149         interrupts:
 150           minItems: 2
 151           maxItems: 2
 152
 153         interrupt-names:
 154           minItems: 2
 155
 156   - if:
 157       properties:
 158         compatible:
 159           contains:
 160             enum:
 161               - qcom,sc7280-cpufreq-epss
 162               - qcom,sm8250-cpufreq-epss
 163               - qcom,sm8350-cpufreq-epss
 164               - qcom,sm8450-cpufreq-epss
 165               - qcom,sm8550-cpufreq-epss
 166     then:
 167       properties:
 168         reg:
 169           minItems: 3
 170           maxItems: 3
 171
 172         reg-names:
 173           minItems: 3
 174           maxItems: 3
 175
 176         interrupts:
 177           minItems: 3
 178           maxItems: 3
 179
 180         interrupt-names:
 181           minItems: 3
 182
 183   - if:
 184       properties:
 185         compatible:
 186           contains:
 187             enum:
 188               - qcom,sm8150-cpufreq-hw
 189     then:
 190       properties:
 191         reg:
 192           minItems: 3
 193           maxItems: 3
 194
 195         reg-names:
 196           minItems: 3
 197           maxItems: 3
 198
 199         # On some SoCs the Prime core shares the LMH irq with Big cores
 200         interrupts:
 201           minItems: 2
 202           maxItems: 2
 203
 204         interrupt-names:
 205           minItems: 2
 206
 207
 208 examples:
 209   - |
 210     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 211     #include <dt-bindings/clock/qcom,rpmh.h>
 212
 213     // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
 214     // switch DCVS state together.
 215     cpus {
 216       #address-cells = <2>;
 217       #size-cells = <0>;
 218
 219       CPU0: cpu@0 {
 220         device_type = "cpu";
 221         compatible = "qcom,kryo385";
 222         reg = <0x0 0x0>;
 223         enable-method = "psci";
 224         next-level-cache = <&L2_0>;
 225         qcom,freq-domain = <&cpufreq_hw 0>;
 226         clocks = <&cpufreq_hw 0>;
 227         L2_0: l2-cache {
 228           compatible = "cache";
 229           cache-unified;
 230           cache-level = <2>;
 231           next-level-cache = <&L3_0>;
 232           L3_0: l3-cache {
 233             compatible = "cache";
 234             cache-unified;
 235             cache-level = <3>;
 236           };
 237         };
 238       };
 239
 240       CPU1: cpu@100 {
 241         device_type = "cpu";
 242         compatible = "qcom,kryo385";
 243         reg = <0x0 0x100>;
 244         enable-method = "psci";
 245         next-level-cache = <&L2_100>;
 246         qcom,freq-domain = <&cpufreq_hw 0>;
 247         clocks = <&cpufreq_hw 0>;
 248         L2_100: l2-cache {
 249           compatible = "cache";
 250           cache-unified;
 251           cache-level = <2>;
 252           next-level-cache = <&L3_0>;
 253         };
 254       };
 255
 256       CPU2: cpu@200 {
 257         device_type = "cpu";
 258         compatible = "qcom,kryo385";
 259         reg = <0x0 0x200>;
 260         enable-method = "psci";
 261         next-level-cache = <&L2_200>;
 262         qcom,freq-domain = <&cpufreq_hw 0>;
 263         clocks = <&cpufreq_hw 0>;
 264         L2_200: l2-cache {
 265           compatible = "cache";
 266           cache-unified;
 267           cache-level = <2>;
 268           next-level-cache = <&L3_0>;
 269         };
 270       };
 271
 272       CPU3: cpu@300 {
 273         device_type = "cpu";
 274         compatible = "qcom,kryo385";
 275         reg = <0x0 0x300>;
 276         enable-method = "psci";
 277         next-level-cache = <&L2_300>;
 278         qcom,freq-domain = <&cpufreq_hw 0>;
 279         clocks = <&cpufreq_hw 0>;
 280         L2_300: l2-cache {
 281           compatible = "cache";
 282           cache-unified;
 283           cache-level = <2>;
 284           next-level-cache = <&L3_0>;
 285         };
 286       };
 287
 288       CPU4: cpu@400 {
 289         device_type = "cpu";
 290         compatible = "qcom,kryo385";
 291         reg = <0x0 0x400>;
 292         enable-method = "psci";
 293         next-level-cache = <&L2_400>;
 294         qcom,freq-domain = <&cpufreq_hw 1>;
 295         clocks = <&cpufreq_hw 1>;
 296         L2_400: l2-cache {
 297           compatible = "cache";
 298           cache-unified;
 299           cache-level = <2>;
 300           next-level-cache = <&L3_0>;
 301         };
 302       };
 303
 304       CPU5: cpu@500 {
 305         device_type = "cpu";
 306         compatible = "qcom,kryo385";
 307         reg = <0x0 0x500>;
 308         enable-method = "psci";
 309         next-level-cache = <&L2_500>;
 310         qcom,freq-domain = <&cpufreq_hw 1>;
 311         clocks = <&cpufreq_hw 1>;
 312         L2_500: l2-cache {
 313           compatible = "cache";
 314           cache-unified;
 315           cache-level = <2>;
 316           next-level-cache = <&L3_0>;
 317         };
 318       };
 319
 320       CPU6: cpu@600 {
 321         device_type = "cpu";
 322         compatible = "qcom,kryo385";
 323         reg = <0x0 0x600>;
 324         enable-method = "psci";
 325         next-level-cache = <&L2_600>;
 326         qcom,freq-domain = <&cpufreq_hw 1>;
 327         clocks = <&cpufreq_hw 1>;
 328         L2_600: l2-cache {
 329           compatible = "cache";
 330           cache-unified;
 331           cache-level = <2>;
 332           next-level-cache = <&L3_0>;
 333         };
 334       };
 335
 336       CPU7: cpu@700 {
 337         device_type = "cpu";
 338         compatible = "qcom,kryo385";
 339         reg = <0x0 0x700>;
 340         enable-method = "psci";
 341         next-level-cache = <&L2_700>;
 342         qcom,freq-domain = <&cpufreq_hw 1>;
 343         clocks = <&cpufreq_hw 1>;
 344         L2_700: l2-cache {
 345           compatible = "cache";
 346           cache-unified;
 347           cache-level = <2>;
 348           next-level-cache = <&L3_0>;
 349         };
 350       };
 351     };
 352
 353     soc {
 354       #address-cells = <1>;
 355       #size-cells = <1>;
 356
 357       cpufreq@17d43000 {
 358         compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
 359         reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
 360         reg-names = "freq-domain0", "freq-domain1";
 361
 362         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
 363         clock-names = "xo", "alternate";
 364
 365         #freq-domain-cells = <1>;
 366         #clock-cells = <1>;
 367       };
 368     };
 369 ...