Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. CPUFREQ
   8
   9 maintainers:
  10   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  11
  12 description: |
  13
  14   CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
  15   SoCs to manage frequency in hardware. It is capable of controlling frequency
  16   for multiple clusters.
  17
  18 properties:
  19   compatible:
  20     oneOf:
  21       - description: v1 of CPUFREQ HW
  22         items:
  23           - const: qcom,cpufreq-hw
  24
  25       - description: v2 of CPUFREQ HW (EPSS)
  26         items:
  27           - enum:
  28               - qcom,sm8250-cpufreq-epss
  29           - const: qcom,cpufreq-epss
  30
  31   reg:
  32     minItems: 2
  33     items:
  34       - description: Frequency domain 0 register region
  35       - description: Frequency domain 1 register region
  36       - description: Frequency domain 2 register region
  37
  38   reg-names:
  39     minItems: 2
  40     items:
  41       - const: freq-domain0
  42       - const: freq-domain1
  43       - const: freq-domain2
  44
  45   clocks:
  46     items:
  47       - description: XO Clock
  48       - description: GPLL0 Clock
  49
  50   clock-names:
  51     items:
  52       - const: xo
  53       - const: alternate
  54
  55   '#freq-domain-cells':
  56     const: 1
  57
  58 required:
  59   - compatible
  60   - reg
  61   - clocks
  62   - clock-names
  63   - '#freq-domain-cells'
  64
  65 additionalProperties: false
  66
  67 examples:
  68   - |
  69     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  70     #include <dt-bindings/clock/qcom,rpmh.h>
  71
  72     // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
  73     // switch DCVS state together.
  74     cpus {
  75       #address-cells = <2>;
  76       #size-cells = <0>;
  77
  78       CPU0: cpu@0 {
  79         device_type = "cpu";
  80         compatible = "qcom,kryo385";
  81         reg = <0x0 0x0>;
  82         enable-method = "psci";
  83         next-level-cache = <&L2_0>;
  84         qcom,freq-domain = <&cpufreq_hw 0>;
  85         L2_0: l2-cache {
  86           compatible = "cache";
  87           next-level-cache = <&L3_0>;
  88           L3_0: l3-cache {
  89             compatible = "cache";
  90           };
  91         };
  92       };
  93
  94       CPU1: cpu@100 {
  95         device_type = "cpu";
  96         compatible = "qcom,kryo385";
  97         reg = <0x0 0x100>;
  98         enable-method = "psci";
  99         next-level-cache = <&L2_100>;
 100         qcom,freq-domain = <&cpufreq_hw 0>;
 101         L2_100: l2-cache {
 102           compatible = "cache";
 103           next-level-cache = <&L3_0>;
 104         };
 105       };
 106
 107       CPU2: cpu@200 {
 108         device_type = "cpu";
 109         compatible = "qcom,kryo385";
 110         reg = <0x0 0x200>;
 111         enable-method = "psci";
 112         next-level-cache = <&L2_200>;
 113         qcom,freq-domain = <&cpufreq_hw 0>;
 114         L2_200: l2-cache {
 115           compatible = "cache";
 116           next-level-cache = <&L3_0>;
 117         };
 118       };
 119
 120       CPU3: cpu@300 {
 121         device_type = "cpu";
 122         compatible = "qcom,kryo385";
 123         reg = <0x0 0x300>;
 124         enable-method = "psci";
 125         next-level-cache = <&L2_300>;
 126         qcom,freq-domain = <&cpufreq_hw 0>;
 127         L2_300: l2-cache {
 128           compatible = "cache";
 129           next-level-cache = <&L3_0>;
 130         };
 131       };
 132
 133       CPU4: cpu@400 {
 134         device_type = "cpu";
 135         compatible = "qcom,kryo385";
 136         reg = <0x0 0x400>;
 137         enable-method = "psci";
 138         next-level-cache = <&L2_400>;
 139         qcom,freq-domain = <&cpufreq_hw 1>;
 140         L2_400: l2-cache {
 141           compatible = "cache";
 142           next-level-cache = <&L3_0>;
 143         };
 144       };
 145
 146       CPU5: cpu@500 {
 147         device_type = "cpu";
 148         compatible = "qcom,kryo385";
 149         reg = <0x0 0x500>;
 150         enable-method = "psci";
 151         next-level-cache = <&L2_500>;
 152         qcom,freq-domain = <&cpufreq_hw 1>;
 153         L2_500: l2-cache {
 154           compatible = "cache";
 155           next-level-cache = <&L3_0>;
 156         };
 157       };
 158
 159       CPU6: cpu@600 {
 160         device_type = "cpu";
 161         compatible = "qcom,kryo385";
 162         reg = <0x0 0x600>;
 163         enable-method = "psci";
 164         next-level-cache = <&L2_600>;
 165         qcom,freq-domain = <&cpufreq_hw 1>;
 166         L2_600: l2-cache {
 167           compatible = "cache";
 168           next-level-cache = <&L3_0>;
 169         };
 170       };
 171
 172       CPU7: cpu@700 {
 173         device_type = "cpu";
 174         compatible = "qcom,kryo385";
 175         reg = <0x0 0x700>;
 176         enable-method = "psci";
 177         next-level-cache = <&L2_700>;
 178         qcom,freq-domain = <&cpufreq_hw 1>;
 179         L2_700: l2-cache {
 180           compatible = "cache";
 181           next-level-cache = <&L3_0>;
 182         };
 183       };
 184     };
 185
 186     soc {
 187       #address-cells = <1>;
 188       #size-cells = <1>;
 189
 190       cpufreq@17d43000 {
 191         compatible = "qcom,cpufreq-hw";
 192         reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
 193         reg-names = "freq-domain0", "freq-domain1";
 194
 195         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
 196         clock-names = "xo", "alternate";
 197
 198         #freq-domain-cells = <1>;
 199       };
 200     };
 201 ...