Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. CPUFREQ
   8
   9 maintainers:
  10   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  11
  12 description: |
  13
  14   CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
  15   SoCs to manage frequency in hardware. It is capable of controlling frequency
  16   for multiple clusters.
  17
  18 properties:
  19   compatible:
  20     oneOf:
  21       - description: v1 of CPUFREQ HW
  22         items:
  23           - const: qcom,cpufreq-hw
  24
  25       - description: v2 of CPUFREQ HW (EPSS)
  26         items:
  27           - enum:
  28               - qcom,sm6375-cpufreq-epss
  29               - qcom,sm8250-cpufreq-epss
  30           - const: qcom,cpufreq-epss
  31
  32   reg:
  33     minItems: 2
  34     items:
  35       - description: Frequency domain 0 register region
  36       - description: Frequency domain 1 register region
  37       - description: Frequency domain 2 register region
  38
  39   reg-names:
  40     minItems: 2
  41     items:
  42       - const: freq-domain0
  43       - const: freq-domain1
  44       - const: freq-domain2
  45
  46   clocks:
  47     items:
  48       - description: XO Clock
  49       - description: GPLL0 Clock
  50
  51   clock-names:
  52     items:
  53       - const: xo
  54       - const: alternate
  55
  56   '#freq-domain-cells':
  57     const: 1
  58
  59 required:
  60   - compatible
  61   - reg
  62   - clocks
  63   - clock-names
  64   - '#freq-domain-cells'
  65
  66 additionalProperties: false
  67
  68 examples:
  69   - |
  70     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
  71     #include <dt-bindings/clock/qcom,rpmh.h>
  72
  73     // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
  74     // switch DCVS state together.
  75     cpus {
  76       #address-cells = <2>;
  77       #size-cells = <0>;
  78
  79       CPU0: cpu@0 {
  80         device_type = "cpu";
  81         compatible = "qcom,kryo385";
  82         reg = <0x0 0x0>;
  83         enable-method = "psci";
  84         next-level-cache = <&L2_0>;
  85         qcom,freq-domain = <&cpufreq_hw 0>;
  86         L2_0: l2-cache {
  87           compatible = "cache";
  88           next-level-cache = <&L3_0>;
  89           L3_0: l3-cache {
  90             compatible = "cache";
  91           };
  92         };
  93       };
  94
  95       CPU1: cpu@100 {
  96         device_type = "cpu";
  97         compatible = "qcom,kryo385";
  98         reg = <0x0 0x100>;
  99         enable-method = "psci";
 100         next-level-cache = <&L2_100>;
 101         qcom,freq-domain = <&cpufreq_hw 0>;
 102         L2_100: l2-cache {
 103           compatible = "cache";
 104           next-level-cache = <&L3_0>;
 105         };
 106       };
 107
 108       CPU2: cpu@200 {
 109         device_type = "cpu";
 110         compatible = "qcom,kryo385";
 111         reg = <0x0 0x200>;
 112         enable-method = "psci";
 113         next-level-cache = <&L2_200>;
 114         qcom,freq-domain = <&cpufreq_hw 0>;
 115         L2_200: l2-cache {
 116           compatible = "cache";
 117           next-level-cache = <&L3_0>;
 118         };
 119       };
 120
 121       CPU3: cpu@300 {
 122         device_type = "cpu";
 123         compatible = "qcom,kryo385";
 124         reg = <0x0 0x300>;
 125         enable-method = "psci";
 126         next-level-cache = <&L2_300>;
 127         qcom,freq-domain = <&cpufreq_hw 0>;
 128         L2_300: l2-cache {
 129           compatible = "cache";
 130           next-level-cache = <&L3_0>;
 131         };
 132       };
 133
 134       CPU4: cpu@400 {
 135         device_type = "cpu";
 136         compatible = "qcom,kryo385";
 137         reg = <0x0 0x400>;
 138         enable-method = "psci";
 139         next-level-cache = <&L2_400>;
 140         qcom,freq-domain = <&cpufreq_hw 1>;
 141         L2_400: l2-cache {
 142           compatible = "cache";
 143           next-level-cache = <&L3_0>;
 144         };
 145       };
 146
 147       CPU5: cpu@500 {
 148         device_type = "cpu";
 149         compatible = "qcom,kryo385";
 150         reg = <0x0 0x500>;
 151         enable-method = "psci";
 152         next-level-cache = <&L2_500>;
 153         qcom,freq-domain = <&cpufreq_hw 1>;
 154         L2_500: l2-cache {
 155           compatible = "cache";
 156           next-level-cache = <&L3_0>;
 157         };
 158       };
 159
 160       CPU6: cpu@600 {
 161         device_type = "cpu";
 162         compatible = "qcom,kryo385";
 163         reg = <0x0 0x600>;
 164         enable-method = "psci";
 165         next-level-cache = <&L2_600>;
 166         qcom,freq-domain = <&cpufreq_hw 1>;
 167         L2_600: l2-cache {
 168           compatible = "cache";
 169           next-level-cache = <&L3_0>;
 170         };
 171       };
 172
 173       CPU7: cpu@700 {
 174         device_type = "cpu";
 175         compatible = "qcom,kryo385";
 176         reg = <0x0 0x700>;
 177         enable-method = "psci";
 178         next-level-cache = <&L2_700>;
 179         qcom,freq-domain = <&cpufreq_hw 1>;
 180         L2_700: l2-cache {
 181           compatible = "cache";
 182           next-level-cache = <&L3_0>;
 183         };
 184       };
 185     };
 186
 187     soc {
 188       #address-cells = <1>;
 189       #size-cells = <1>;
 190
 191       cpufreq@17d43000 {
 192         compatible = "qcom,cpufreq-hw";
 193         reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
 194         reg-names = "freq-domain0", "freq-domain1";
 195
 196         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
 197         clock-names = "xo", "alternate";
 198
 199         #freq-domain-cells = <1>;
 200       };
 201     };
 202 ...