1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@xilinx.com>
11 - Jolly Shah <jolly.shah@xilinx.com>
12 - Rajan Vaja <rajan.vaja@xilinx.com>
15 The clock controller is a hardware block of Xilinx versal clock tree. It
16 reads required input clock frequencies from the devicetree and acts as clock
17 provider for all clock consumers of PS clocks.
21 const: xlnx,versal-clk
27 description: List of clock specifiers which are external input
28 clocks to the given clock controller.
30 - description: reference clock
31 - description: alternate reference clock
32 - description: alternate reference clock for programmable logic
46 additionalProperties: false
51 zynqmp_firmware: zynqmp-firmware {
52 compatible = "xlnx,zynqmp-firmware";
54 versal_clk: clock-controller {
56 compatible = "xlnx,versal-clk";
57 clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
58 clock-names = "ref", "alt_ref", "pl_alt_ref";