1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@amd.com>
13 The clock controller is a hardware block of Xilinx versal clock tree. It
14 reads required input clock frequencies from the devicetree and acts as clock
15 provider for all clock consumers of PS clocks.
26 - const: xlnx,versal-clk
32 description: List of clock specifiers which are external input
33 clocks to the given clock controller.
47 additionalProperties: false
61 - description: reference clock
62 - description: alternate reference clock
63 - description: alternate reference clock for programmable logic
83 - description: PS reference clock
84 - description: reference clock for video system
85 - description: alternative PS reference clock
86 - description: auxiliary reference clock
87 - description: transceiver reference clock
88 - description: (E)MIO clock source (Optional clock)
89 - description: GEM emio clock (Optional clock)
90 - description: Watchdog external clock (Optional clock)
97 - const: pss_alt_ref_clk
99 - const: gt_crx_ref_clk
100 - pattern: "^mio_clk[00-77]+.*$"
101 - pattern: "gem[0-3]+_emio_clk.*$"
102 - pattern: "swdt[0-1]+_ext_clk.*$"
107 zynqmp_firmware: zynqmp-firmware {
108 compatible = "xlnx,zynqmp-firmware";
110 versal_clk: clock-controller {
112 compatible = "xlnx,versal-clk";
113 clocks = <&ref>, <&alt_ref>, <&pl_alt_ref>;
114 clock-names = "ref", "alt_ref", "pl_alt_ref";
121 compatible = "xlnx,zynqmp-clk";
122 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
123 <&aux_ref_clk>, <>_crx_ref_clk>;
124 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
125 "aux_ref_clk", "gt_crx_ref_clk";