1 Binding for Texas Instruments DPLL clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. It assumes a
6 register-mapped DPLL with usually two selectable input clocks
7 (reference clock and bypass clock), with digital phase locked
8 loop logic for multiplying the input clock to a desired output
9 clock. This clock also typically supports different operation
10 modes (locked, low power stop etc.) This binding has several
11 sub-types, which effectively result in slightly different setup
12 for the actual DPLL clock.
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
25 "ti,omap4-dpll-m4xen-clock",
26 "ti,omap4-dpll-j-type-clock",
27 "ti,omap5-mpu-dpll-clock",
28 "ti,am3-dpll-no-gate-clock",
29 "ti,am3-dpll-j-type-clock",
30 "ti,am3-dpll-no-gate-j-type-clock",
32 "ti,am3-dpll-core-clock",
33 "ti,am3-dpll-x2-clock",
34 "ti,omap2-dpll-core-clock",
36 - #clock-cells : from common clock binding; shall be set to 0.
37 - clocks : link phandles of parent clocks, first entry lists reference clock
38 and second entry bypass clock
39 - reg : offsets for the register set for controlling the DPLL.
40 Registers are listed in following order:
41 "control" - contains the control register base address
42 "idlest" - contains the idle status register base address
43 "mult-div1" - contains the multiplier / divider register base address
44 "autoidle" - contains the autoidle register base address (optional)
45 "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
46 the frequency spreading register base address (optional)
47 "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
48 the modulation frequency register base address
50 ti,am3-* dpll types do not have autoidle register
51 ti,omap2-* dpll type does not support idlest / autoidle registers
54 - DPLL mode setting - defining any one or more of the following overrides
56 - ti,low-power-stop : DPLL supports low power stop mode, gating output
57 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
58 - ti,lock : DPLL locks in programmed rate
59 - ti,min-div : the minimum divisor to start from to round the DPLL
61 - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
62 spreading in permille (10th of a percent)
63 - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
64 spectrum modulation frequency
65 - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
66 to enable the downspread feature
69 dpll_core_ck: dpll_core_ck@44e00490 {
71 compatible = "ti,omap4-dpll-core-clock";
72 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
73 reg = <0x490>, <0x45c>, <0x488>, <0x468>;
76 dpll2_ck: dpll2_ck@48004004 {
78 compatible = "ti,omap3-dpll-clock";
79 clocks = <&sys_ck>, <&dpll2_fck>;
83 reg = <0x4>, <0x24>, <0x34>, <0x40>;
86 dpll_core_ck: dpll_core_ck@44e00490 {
88 compatible = "ti,am3-dpll-core-clock";
89 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
90 reg = <0x90>, <0x5c>, <0x68>;
95 compatible = "ti,omap2-dpll-core-clock";
96 clocks = <&sys_ck>, <&sys_ck>;
97 reg = <0x0500>, <0x0540>;
100 dpll_disp_ck: dpll_disp_ck {
102 compatible = "ti,am3-dpll-no-gate-clock";
103 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
104 reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;