1 Allwinner Display Engine 2.0 Clock Control Binding
2 --------------------------------------------------
5 - compatible: must contain one of the following compatibles:
6 - "allwinner,sun8i-a83t-de2-clk"
7 - "allwinner,sun8i-v3s-de2-clk"
8 - "allwinner,sun50i-h5-de2-clk"
10 - reg: Must contain the registers base address and length
11 - clocks: phandle to the clocks feeding the display engine subsystem.
13 - "mod": the display engine module clock
14 - "bus": the bus clock for the whole display engine subsystem
15 - clock-names: Must contain the clock names described just above
16 - resets: phandle to the reset control for the display engine subsystem.
17 - #clock-cells : must contain 1
18 - #reset-cells : must contain 1
21 de2_clocks: clock@1000000 {
22 compatible = "allwinner,sun8i-a83t-de2-clk";
23 reg = <0x01000000 0x100000>;
24 clocks = <&ccu CLK_BUS_DE>,
28 resets = <&ccu RST_BUS_DE>;