1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
13 description: While named "U8500 clocks" these clocks are inside the
14 DB8500 digital baseband system-on-chip and its siblings such as
15 DB8520. These bindings consider the clocks present in the SoC
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
18 control management unit) clocks and PRCC (peripheral reset and
19 clock controller) clocks. For some reason PRCC 4 does not exist so
20 the itemization can be a bit unintuitive.
25 - stericsson,u8500-clks
26 - stericsson,u8540-clks
27 - stericsson,u9540-clks
31 - description: PRCC 1 register area
32 - description: PRCC 2 register area
33 - description: PRCC 3 register area
34 - description: PRCC 5 register area
35 - description: PRCC 6 register area
38 description: A subnode with one clock cell for PRCMU (power, reset, control
39 management unit) clocks. The cell indicates which PRCMU clock in the
40 prcmu-clock node the consumer wants to use.
47 additionalProperties: false
50 description: A subnode with two clock cells for PRCC (peripheral
51 reset and clock controller) peripheral clocks. The first cell indicates
52 which PRCC block the consumer wants to use, possible values are 1, 2, 3,
53 5, 6. The second cell indicates which clock inside the PRCC block it
54 wants, possible values are 0 thru 31.
61 additionalProperties: false
64 description: A subnode with two clock cells for PRCC (peripheral reset
65 and clock controller) kernel clocks. The first cell indicates which PRCC
66 block the consumer wants to use, possible values are 1, 2, 3, 5, 6. The
67 second cell indicates which clock inside the PRCC block it wants, possible
75 additionalProperties: false
77 prcc-reset-controller:
78 description: A subnode with two reset cells for the reset portions of the
79 PRCC (peripheral reset and clock controller). The first cell indicates
80 which PRCC block the consumer wants to use, possible values are 1, 2, 3
81 5 and 6. The second cell indicates which reset line inside the PRCC block
82 it wants to control, possible values are 0 thru 31.
89 additionalProperties: false
92 description: A subnode with zero clock cells for the 32kHz RTC clock.
99 additionalProperties: false
102 description: A subnode for the ARM SMP Timer Watchdog cluster with zero
110 additionalProperties: false
113 description: A subnode with three clock cells for externally routed clocks,
114 output clocks. These are two PRCMU-internal clocks that can be divided and
115 muxed out on the pads of the DB8500 SoC.
121 The first cell indicates which output clock we are using,
122 possible values are 0 (CLKOUT1) and 1 (CLKOUT2).
123 The second cell indicates which clock we want to use as source,
124 possible values are 0 thru 7, see the defines for the different
126 The third cell is a divider, legal values are 1 thru 63.
129 additionalProperties: false
140 additionalProperties: false
144 #include <dt-bindings/clock/ste-db8500-clkout.h>
146 compatible = "stericsson,u8500-clks";
147 reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
148 <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
151 prcmu_clk: prcmu-clock {
155 prcc_pclk: prcc-periph-clock {
159 prcc_kclk: prcc-kernel-clock {
163 prcc_reset: prcc-reset-controller {
167 rtc_clk: rtc32k-clock {
171 smp_twd_clk: smp-twd-clock {
175 clkout_clk: clkout-clock {