1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 System-Top-Group Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-stgcrg
21 - description: Main Oscillator (24 MHz)
22 - description: HIFI4 core
23 - description: STG AXI/AHB
24 - description: USB (125 MHz)
25 - description: CPU Bus
26 - description: HIFI4 Axi
27 - description: NOC STG Bus
28 - description: APB Bus
44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
59 additionalProperties: false
63 #include <dt-bindings/clock/starfive,jh7110-crg.h>
65 stgcrg: clock-controller@10230000 {
66 compatible = "starfive,jh7110-stgcrg";
67 reg = <0x10230000 0x10000>;
69 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
70 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
71 <&syscrg JH7110_SYSCLK_USB_125M>,
72 <&syscrg JH7110_SYSCLK_CPU_BUS>,
73 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
74 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
75 <&syscrg JH7110_SYSCLK_APB_BUS>;
76 clock-names = "osc", "hifi4_core",
77 "stg_axiahb", "usb_125m",
78 "cpu_bus", "hifi4_axi",
79 "nocstg_bus", "apb_bus";