1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PLL Clock Generator
10 These PLLs are high speed, low jitter frequency synthesizers in the JH7110.
11 Each PLL works in integer mode or fraction mode, with configuration
12 registers in the sys syscon. So the PLLs node should be a child of
14 The formula for calculating frequency is
15 Fvco = Fref * (NI + NF) / M / Q1
18 - Xingyu Wu <xingyu.wu@starfivetech.com>
22 const: starfive,jh7110-pll
26 description: Main Oscillator (24 MHz)
31 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
38 additionalProperties: false
43 compatible = "starfive,jh7110-pll";